Author: tstellar
Date: Mon Apr  9 13:45:48 2018
New Revision: 329619

URL: http://llvm.org/viewvc/llvm-project?rev=329619&view=rev
Log:
Merging r322319:

------------------------------------------------------------------------
r322319 | matze | 2018-01-11 14:30:43 -0800 (Thu, 11 Jan 2018) | 7 lines

PeepholeOptimizer: Fix for vregs without defs

The PeepholeOptimizer would fail for vregs without a definition. If this
was caused by an undef operand abort to keep the code simple (so we
don't need to add logic everywhere to replicate the undef flag).

Differential Revision: https://reviews.llvm.org/D40763
------------------------------------------------------------------------

Modified:
    llvm/branches/release_60/include/llvm/CodeGen/TargetInstrInfo.h
    llvm/branches/release_60/lib/CodeGen/PeepholeOptimizer.cpp
    llvm/branches/release_60/lib/CodeGen/TargetInstrInfo.cpp
    llvm/branches/release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/branches/release_60/test/CodeGen/ARM/peephole-phi.mir

Modified: llvm/branches/release_60/include/llvm/CodeGen/TargetInstrInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/include/llvm/CodeGen/TargetInstrInfo.h?rev=329619&r1=329618&r2=329619&view=diff
==============================================================================
--- llvm/branches/release_60/include/llvm/CodeGen/TargetInstrInfo.h (original)
+++ llvm/branches/release_60/include/llvm/CodeGen/TargetInstrInfo.h Mon Apr  9 
13:45:48 2018
@@ -421,7 +421,8 @@ public:
   /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
   /// and \p DefIdx.
   /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
-  /// the list is modeled as <Reg:SubReg, SubIdx>.
+  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
+  /// flag are not added to this list.
   /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
   /// two elements:
   /// - %1:sub1, sub0
@@ -446,7 +447,8 @@ public:
   /// - %1:sub1, sub0
   ///
   /// \returns true if it is possible to build such an input sequence
-  /// with the pair \p MI, \p DefIdx. False otherwise.
+  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
+  /// False otherwise.
   ///
   /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
   ///
@@ -465,7 +467,8 @@ public:
   /// - InsertedReg: %1:sub1, sub3
   ///
   /// \returns true if it is possible to build such an input sequence
-  /// with the pair \p MI, \p DefIdx. False otherwise.
+  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
+  /// False otherwise.
   ///
   /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
   ///

Modified: llvm/branches/release_60/lib/CodeGen/PeepholeOptimizer.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/CodeGen/PeepholeOptimizer.cpp?rev=329619&r1=329618&r2=329619&view=diff
==============================================================================
--- llvm/branches/release_60/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/branches/release_60/lib/CodeGen/PeepholeOptimizer.cpp Mon Apr  9 
13:45:48 2018
@@ -1882,6 +1882,8 @@ ValueTrackerResult ValueTracker::getNext
     return ValueTrackerResult();
   // Otherwise, we want the whole source.
   const MachineOperand &Src = Def->getOperand(1);
+  if (Src.isUndef())
+    return ValueTrackerResult();
   return ValueTrackerResult(Src.getReg(), Src.getSubReg());
 }
 
@@ -1925,6 +1927,8 @@ ValueTrackerResult ValueTracker::getNext
   }
 
   const MachineOperand &Src = Def->getOperand(SrcIdx);
+  if (Src.isUndef())
+    return ValueTrackerResult();
   return ValueTrackerResult(Src.getReg(), Src.getSubReg());
 }
 
@@ -2093,6 +2097,10 @@ ValueTrackerResult ValueTracker::getNext
   for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
     auto &MO = Def->getOperand(i);
     assert(MO.isReg() && "Invalid PHI instruction");
+    // We have no code to deal with undef operands. They shouldn't happen in
+    // normal programs anyway.
+    if (MO.isUndef())
+      return ValueTrackerResult();
     Res.addSource(MO.getReg(), MO.getSubReg());
   }
 
@@ -2149,9 +2157,14 @@ ValueTrackerResult ValueTracker::getNext
     // If we can still move up in the use-def chain, move to the next
     // definition.
     if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
-      Def = MRI.getVRegDef(Reg);
-      DefIdx = MRI.def_begin(Reg).getOperandNo();
-      DefSubReg = Res.getSrcSubReg(0);
+      MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
+      if (DI != MRI.def_end()) {
+        Def = DI->getParent();
+        DefIdx = DI.getOperandNo();
+        DefSubReg = Res.getSrcSubReg(0);
+      } else {
+        Def = nullptr;
+      }
       return Res;
     }
   }

Modified: llvm/branches/release_60/lib/CodeGen/TargetInstrInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/CodeGen/TargetInstrInfo.cpp?rev=329619&r1=329618&r2=329619&view=diff
==============================================================================
--- llvm/branches/release_60/lib/CodeGen/TargetInstrInfo.cpp (original)
+++ llvm/branches/release_60/lib/CodeGen/TargetInstrInfo.cpp Mon Apr  9 
13:45:48 2018
@@ -1151,6 +1151,8 @@ bool TargetInstrInfo::getRegSequenceInpu
   for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
        OpIdx += 2) {
     const MachineOperand &MOReg = MI.getOperand(OpIdx);
+    if (MOReg.isUndef())
+      continue;
     const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
     assert(MOSubIdx.isImm() &&
            "One of the subindex of the reg_sequence is not an immediate");
@@ -1174,6 +1176,8 @@ bool TargetInstrInfo::getExtractSubregIn
   // Def = EXTRACT_SUBREG v0.sub1, sub0.
   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
   const MachineOperand &MOReg = MI.getOperand(1);
+  if (MOReg.isUndef())
+    return false;
   const MachineOperand &MOSubIdx = MI.getOperand(2);
   assert(MOSubIdx.isImm() &&
          "The subindex of the extract_subreg is not an immediate");
@@ -1198,6 +1202,8 @@ bool TargetInstrInfo::getInsertSubregInp
   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
   const MachineOperand &MOBaseReg = MI.getOperand(1);
   const MachineOperand &MOInsertedReg = MI.getOperand(2);
+  if (MOInsertedReg.isUndef())
+    return false;
   const MachineOperand &MOSubIdx = MI.getOperand(3);
   assert(MOSubIdx.isImm() &&
          "One of the subindex of the reg_sequence is not an immediate");

Modified: llvm/branches/release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=329619&r1=329618&r2=329619&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Apr  9 
13:45:48 2018
@@ -4864,12 +4864,14 @@ bool ARMBaseInstrInfo::getRegSequenceLik
     // Populate the InputRegs accordingly.
     // rY
     const MachineOperand *MOReg = &MI.getOperand(1);
-    InputRegs.push_back(
-        RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
+    if (!MOReg->isUndef())
+      InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
+                                              MOReg->getSubReg(), 
ARM::ssub_0));
     // rZ
     MOReg = &MI.getOperand(2);
-    InputRegs.push_back(
-        RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
+    if (!MOReg->isUndef())
+      InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
+                                              MOReg->getSubReg(), 
ARM::ssub_1));
     return true;
   }
   llvm_unreachable("Target dependent opcode missing");
@@ -4888,6 +4890,8 @@ bool ARMBaseInstrInfo::getExtractSubregL
     // rX = EXTRACT_SUBREG dZ, ssub_0
     // rY = EXTRACT_SUBREG dZ, ssub_1
     const MachineOperand &MOReg = MI.getOperand(2);
+    if (MOReg.isUndef())
+      return false;
     InputReg.Reg = MOReg.getReg();
     InputReg.SubReg = MOReg.getSubReg();
     InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
@@ -4907,6 +4911,8 @@ bool ARMBaseInstrInfo::getInsertSubregLi
     // dX = VSETLNi32 dY, rZ, imm
     const MachineOperand &MOBaseReg = MI.getOperand(1);
     const MachineOperand &MOInsertedReg = MI.getOperand(2);
+    if (MOInsertedReg.isUndef())
+      return false;
     const MachineOperand &MOIndex = MI.getOperand(3);
     BaseReg.Reg = MOBaseReg.getReg();
     BaseReg.SubReg = MOBaseReg.getSubReg();

Modified: llvm/branches/release_60/test/CodeGen/ARM/peephole-phi.mir
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/ARM/peephole-phi.mir?rev=329619&r1=329618&r2=329619&view=diff
==============================================================================
--- llvm/branches/release_60/test/CodeGen/ARM/peephole-phi.mir (original)
+++ llvm/branches/release_60/test/CodeGen/ARM/peephole-phi.mir Mon Apr  9 
13:45:48 2018
@@ -65,3 +65,39 @@ body: |
     %4:gpr = PHI %0, %bb.1, %2, %bb.2
     %5:spr = VMOVSR %4, 14, %noreg
 ...
+
+# The current implementation doesn't perform any transformations if undef
+# operands are involved.
+# CHECK-LABEL: name: func-undefops
+# CHECK: body: |
+# CHECK:   bb.0:
+# CHECK:     Bcc %bb.2, 1, undef %cpsr
+#
+# CHECK:   bb.1:
+# CHECK:     %0:gpr = VMOVRS undef %1:spr, 14, %noreg
+# CHECK:     B %bb.3
+#
+# CHECK:   bb.2:
+# CHECK:     %2:gpr = VMOVRS undef %3:spr, 14, %noreg
+#
+# CHECK:   bb.3:
+# CHECK:     %4:gpr = PHI %0, %bb.1, %2, %bb.2
+# CHECK:     %5:spr = VMOVSR %4, 14, %noreg
+---
+name: func-undefops
+tracksRegLiveness: true
+body: |
+  bb.0:
+    Bcc %bb.2, 1, undef %cpsr
+
+  bb.1:
+    %0:gpr = VMOVRS undef %1:spr, 14, %noreg
+    B %bb.3
+
+  bb.2:
+    %2:gpr = VMOVRS undef %3:spr, 14, %noreg
+
+  bb.3:
+    %4:gpr = PHI %0, %bb.1, %2, %bb.2
+    %5:spr = VMOVSR %4, 14, %noreg
+...


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