Author: tstellar
Date: Wed May 16 19:15:24 2018
New Revision: 332565
URL: http://llvm.org/viewvc/llvm-project?rev=332565&view=rev
Log:
Merging r329414:
------------------------------------------------------------------------
r329414 | ctopper | 2018-04-06 09:16:43 -0700 (Fri, 06 Apr 2018) | 3 lines
[X86] Merge itineraries for CLC, CMC, and STC.
These are very simple flag setting instructions that appear to only be a single
uop. They're unlikely to need this separation.
------------------------------------------------------------------------
Modified:
llvm/branches/release_60/lib/Target/X86/X86InstrInfo.td
llvm/branches/release_60/lib/Target/X86/X86Schedule.td
llvm/branches/release_60/lib/Target/X86/X86ScheduleAtom.td
Modified: llvm/branches/release_60/lib/Target/X86/X86InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86InstrInfo.td?rev=332565&r1=332564&r2=332565&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/release_60/lib/Target/X86/X86InstrInfo.td Wed May 16 19:15:24
2018
@@ -2119,13 +2119,13 @@ def INSL : I<0x6D, RawFrmDst, (outs), (i
// Flag instructions
let SchedRW = [WriteALU] in {
-def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
-def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
+def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC_CMC_STC>;
+def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_CLC_CMC_STC>;
def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
-def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
+def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>;
def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
}
Modified: llvm/branches/release_60/lib/Target/X86/X86Schedule.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86Schedule.td?rev=332565&r1=332564&r2=332565&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/X86/X86Schedule.td (original)
+++ llvm/branches/release_60/lib/Target/X86/X86Schedule.td Wed May 16 19:15:24
2018
@@ -608,12 +608,10 @@ def IIC_CMPXCHG_8B : InstrItinClass;
def IIC_CMPXCHG_16B : InstrItinClass;
def IIC_LODS : InstrItinClass;
def IIC_OUTS : InstrItinClass;
-def IIC_CLC : InstrItinClass;
+def IIC_CLC_CMC_STC : InstrItinClass;
def IIC_CLD : InstrItinClass;
def IIC_CLI : InstrItinClass;
-def IIC_CMC : InstrItinClass;
def IIC_CLTS : InstrItinClass;
-def IIC_STC : InstrItinClass;
def IIC_STI : InstrItinClass;
def IIC_STD : InstrItinClass;
def IIC_XLAT : InstrItinClass;
Modified: llvm/branches/release_60/lib/Target/X86/X86ScheduleAtom.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86ScheduleAtom.td?rev=332565&r1=332564&r2=332565&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/branches/release_60/lib/Target/X86/X86ScheduleAtom.td Wed May 16
19:15:24 2018
@@ -514,12 +514,10 @@ def AtomItineraries : ProcessorItinerari
InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >,
InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >,
- InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >,
+ InstrItinData<IIC_CLC_CMC_STC, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >,
- InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >,
- InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >,
InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >,
InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >,
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