Author: hans Date: Wed Aug 28 06:58:21 2019 New Revision: 370205 URL: http://llvm.org/viewvc/llvm-project?rev=370205&view=rev Log: Merging r370204: ------------------------------------------------------------------------ r370204 | hans | 2019-08-28 15:55:10 +0200 (Wed, 28 Aug 2019) | 6 lines
[SelectionDAG] Don't generate libcalls for wide shifts on Windows (PR42711) Neither libgcc or compiler-rt are usually used on Windows, so these functions can't be called. Differential revision: https://reviews.llvm.org/D66880 ------------------------------------------------------------------------ Modified: llvm/branches/release_90/ (props changed) llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.h llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp llvm/branches/release_90/lib/Target/X86/X86ISelLowering.h llvm/branches/release_90/test/CodeGen/AArch64/shift_minsize.ll llvm/branches/release_90/test/CodeGen/X86/shift_minsize.ll Propchange: llvm/branches/release_90/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Wed Aug 28 06:58:21 2019 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369426,369443,369886,370036,370176 +/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369426,369443,369886,370036,370176,370204 Modified: llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=370205&r1=370204&r2=370205&view=diff ============================================================================== --- llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp (original) +++ llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Aug 28 06:58:21 2019 @@ -11995,6 +11995,14 @@ bool AArch64TargetLowering::isMaskAndCmp return Mask->getValue().isPowerOf2(); } +bool AArch64TargetLowering::shouldExpandShift(SelectionDAG &DAG, + SDNode *N) const { + if (DAG.getMachineFunction().getFunction().hasMinSize() && + !Subtarget->isTargetWindows()) + return false; + return true; +} + void AArch64TargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const { // Update IsSplitCSR in AArch64unctionInfo. AArch64FunctionInfo *AFI = Entry->getParent()->getInfo<AArch64FunctionInfo>(); Modified: llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.h?rev=370205&r1=370204&r2=370205&view=diff ============================================================================== --- llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.h (original) +++ llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.h Wed Aug 28 06:58:21 2019 @@ -480,11 +480,7 @@ public: return VT.getSizeInBits() >= 64; // vector 'bic' } - bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { - if (DAG.getMachineFunction().getFunction().hasMinSize()) - return false; - return true; - } + bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override; bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override { Modified: llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp?rev=370205&r1=370204&r2=370205&view=diff ============================================================================== --- llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp Wed Aug 28 06:58:21 2019 @@ -5059,6 +5059,14 @@ bool X86TargetLowering::shouldFoldMaskTo return true; } +bool X86TargetLowering::shouldExpandShift(SelectionDAG &DAG, + SDNode *N) const { + if (DAG.getMachineFunction().getFunction().hasMinSize() && + !Subtarget.isOSWindows()) + return false; + return true; +} + bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const { // Any legal vector type can be splatted more efficiently than // loading/spilling from memory. Modified: llvm/branches/release_90/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/X86/X86ISelLowering.h?rev=370205&r1=370204&r2=370205&view=diff ============================================================================== --- llvm/branches/release_90/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/branches/release_90/lib/Target/X86/X86ISelLowering.h Wed Aug 28 06:58:21 2019 @@ -863,11 +863,7 @@ namespace llvm { return VTIsOk(XVT) && VTIsOk(KeptBitsVT); } - bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { - if (DAG.getMachineFunction().getFunction().hasMinSize()) - return false; - return true; - } + bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override; bool shouldSplatInsEltVarIndex(EVT VT) const override; Modified: llvm/branches/release_90/test/CodeGen/AArch64/shift_minsize.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/shift_minsize.ll?rev=370205&r1=370204&r2=370205&view=diff ============================================================================== --- llvm/branches/release_90/test/CodeGen/AArch64/shift_minsize.ll (original) +++ llvm/branches/release_90/test/CodeGen/AArch64/shift_minsize.ll Wed Aug 28 06:58:21 2019 @@ -1,5 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s +; RUN: llc < %s -mtriple=aarch64-windows | FileCheck %s -check-prefix=CHECK-WIN + +; The Windows runtime doesn't have these. +; CHECK-WIN-NOT: __ashlti3 +; CHECK-WIN-NOT: __ashrti3 define i64 @f0(i64 %val, i64 %amt) minsize optsize { ; CHECK-LABEL: f0: @@ -53,6 +58,7 @@ define dso_local { i64, i64 } @shl128(i6 ; CHECK-NEXT: bl __ashlti3 ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret + entry: %x.sroa.2.0.insert.ext = zext i64 %x.coerce1 to i128 %x.sroa.2.0.insert.shift = shl nuw i128 %x.sroa.2.0.insert.ext, 64 Modified: llvm/branches/release_90/test/CodeGen/X86/shift_minsize.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/X86/shift_minsize.ll?rev=370205&r1=370204&r2=370205&view=diff ============================================================================== --- llvm/branches/release_90/test/CodeGen/X86/shift_minsize.ll (original) +++ llvm/branches/release_90/test/CodeGen/X86/shift_minsize.ll Wed Aug 28 06:58:21 2019 @@ -1,5 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s +; RUN: llc < %s -mtriple=x86_64--windows-msvc | FileCheck %s -check-prefix=CHECK-WIN + +; The Windows runtime doesn't have these. +; CHECK-WIN-NOT: __ashlti3 +; CHECK-WIN-NOT: __ashrti3 +; CHECK-WIN-NOT: __lshrti3 define i64 @f0(i64 %val, i64 %amt) minsize optsize { ; CHECK-LABEL: f0: _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
