Author: Andrei Safronov Date: 2020-07-21T13:25:47+03:00 New Revision: f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3
URL: https://github.com/llvm/llvm-project/commit/f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3 DIFF: https://github.com/llvm/llvm-project/commit/f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3.diff LOG: [Xtensa] Recognize Xtensa in triple parsing code. Added: Modified: clang/lib/CodeGen/CGOpenMPRuntime.cpp llvm/include/llvm/ADT/Triple.h llvm/lib/Support/Triple.cpp llvm/unittests/ADT/TripleTest.cpp Removed: ################################################################################ diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 97b17799a03e..bd4ca476b7b5 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -11118,6 +11118,7 @@ bool checkContext<OMP_CTX_SET_device, OMP_CTX_kind, CodeGenModule &>( case llvm::Triple::renderscript32: case llvm::Triple::renderscript64: case llvm::Triple::ve: + case llvm::Triple::xtensa: return false; } } diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h index 76a754d671fb..eed0ee0de34c 100644 --- a/llvm/include/llvm/ADT/Triple.h +++ b/llvm/include/llvm/ADT/Triple.h @@ -78,6 +78,7 @@ class Triple { x86, // X86: i[3-9]86 x86_64, // X86-64: amd64, x86_64 xcore, // XCore: xcore + xtensa, // Tensilica Xtensa nvptx, // NVPTX: 32-bit nvptx64, // NVPTX: 64-bit le32, // le32: generic little-endian 32-bit CPU (PNaCl) diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp index 2c480c1094a5..6349b9fbeff9 100644 --- a/llvm/lib/Support/Triple.cpp +++ b/llvm/lib/Support/Triple.cpp @@ -71,6 +71,7 @@ StringRef Triple::getArchTypeName(ArchType Kind) { case x86: return "i386"; case x86_64: return "x86_64"; case xcore: return "xcore"; + case xtensa: return "xtensa"; } llvm_unreachable("Invalid ArchType!"); @@ -147,6 +148,8 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) { case riscv64: return "riscv"; case ve: return "ve"; + + case xtensa: return "xtensa"; } } @@ -317,6 +320,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { .Case("renderscript32", renderscript32) .Case("renderscript64", renderscript64) .Case("ve", ve) + .Case("xtensa", xtensa) .Default(UnknownArch); } @@ -446,6 +450,7 @@ static Triple::ArchType parseArch(StringRef ArchName) { .Case("ve", Triple::ve) .Case("wasm32", Triple::wasm32) .Case("wasm64", Triple::wasm64) + .Case("xtensa", Triple::xtensa) .Default(Triple::UnknownArch); // Some architectures require special parsing logic just to compute the @@ -706,6 +711,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) { case Triple::thumbeb: case Triple::ve: case Triple::xcore: + case Triple::xtensa: return Triple::ELF; case Triple::ppc64: @@ -1267,6 +1273,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) { case llvm::Triple::wasm32: case llvm::Triple::x86: case llvm::Triple::xcore: + case llvm::Triple::xtensa: return 32; case llvm::Triple::aarch64: @@ -1350,6 +1357,7 @@ Triple Triple::get32BitArchVariant() const { case Triple::wasm32: case Triple::x86: case Triple::xcore: + case Triple::xtensa: // Already 32-bit. break; @@ -1388,6 +1396,7 @@ Triple Triple::get64BitArchVariant() const { case Triple::tce: case Triple::tcele: case Triple::xcore: + case Triple::xtensa: T.setArch(UnknownArch); break; @@ -1471,6 +1480,7 @@ Triple Triple::getBigEndianArchVariant() const { case Triple::x86_64: case Triple::xcore: case Triple::ve: + case Triple::xtensa: // ARM is intentionally unsupported here, changing the architecture would // drop any arch suffixes. @@ -1563,6 +1573,7 @@ bool Triple::isLittleEndian() const { case Triple::x86: case Triple::x86_64: case Triple::xcore: + case Triple::xtensa: return true; default: return false; diff --git a/llvm/unittests/ADT/TripleTest.cpp b/llvm/unittests/ADT/TripleTest.cpp index ef7f82d268e2..3fd30e4c009d 100644 --- a/llvm/unittests/ADT/TripleTest.cpp +++ b/llvm/unittests/ADT/TripleTest.cpp @@ -579,6 +579,18 @@ TEST(TripleTest, ParsedIDs) { EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); EXPECT_TRUE(T.isArch32Bit()); + T = Triple("xtensa"); + EXPECT_EQ(Triple::xtensa, T.getArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::UnknownOS, T.getOS()); + EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); + + T = Triple("xtensa-unknown-unknown"); + EXPECT_EQ(Triple::xtensa, T.getArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::UnknownOS, T.getOS()); + EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); + T = Triple("huh"); EXPECT_EQ(Triple::UnknownArch, T.getArch()); } @@ -904,6 +916,11 @@ TEST(TripleTest, BitWidthPredicates) { EXPECT_FALSE(T.isArch32Bit()); EXPECT_TRUE(T.isArch64Bit()); EXPECT_TRUE(T.isRISCV()); + + T.setArch(Triple::xtensa); + EXPECT_FALSE(T.isArch16Bit()); + EXPECT_TRUE(T.isArch32Bit()); + EXPECT_FALSE(T.isArch64Bit()); } TEST(TripleTest, BitWidthArchVariants) { @@ -1050,6 +1067,10 @@ TEST(TripleTest, BitWidthArchVariants) { T.setArch(Triple::xcore); EXPECT_EQ(Triple::xcore, T.get32BitArchVariant().getArch()); EXPECT_EQ(Triple::UnknownArch, T.get64BitArchVariant().getArch()); + + T.setArch(Triple::xtensa); + EXPECT_EQ(Triple::xtensa, T.get32BitArchVariant().getArch()); + EXPECT_EQ(Triple::UnknownArch, T.get64BitArchVariant().getArch()); } TEST(TripleTest, EndianArchVariants) { _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
