Author: Evgeny Leviant Date: 2020-12-07T11:53:33+03:00 New Revision: 53401e8e88641941fee0876d234f9a9fc70ef6ce
URL: https://github.com/llvm/llvm-project/commit/53401e8e88641941fee0876d234f9a9fc70ef6ce DIFF: https://github.com/llvm/llvm-project/commit/53401e8e88641941fee0876d234f9a9fc70ef6ce.diff LOG: [TableGen][SchedModels] Simplify the code. NFC Differential revision: https://reviews.llvm.org/D92304 Added: Modified: llvm/utils/TableGen/CodeGenSchedule.cpp llvm/utils/TableGen/CodeGenSchedule.h llvm/utils/TableGen/SubtargetEmitter.cpp Removed: ################################################################################ diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp index 50ee9462d1d1..49a7575dce95 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -1314,16 +1314,12 @@ struct PredTransition { SmallVector<PredCheck, 4> PredTerm; SmallVector<SmallVector<unsigned,4>, 16> WriteSequences; SmallVector<SmallVector<unsigned,4>, 16> ReadSequences; - SmallVector<unsigned, 4> ProcIndices; + unsigned ProcIndex = 0; PredTransition() = default; - PredTransition(ArrayRef<PredCheck> PT) { + PredTransition(ArrayRef<PredCheck> PT, unsigned ProcId) { PredTerm.assign(PT.begin(), PT.end()); - ProcIndices.assign(1, 0); - } - PredTransition(ArrayRef<PredCheck> PT, ArrayRef<unsigned> PIds) { - PredTerm.assign(PT.begin(), PT.end()); - ProcIndices.assign(PIds.begin(), PIds.end()); + ProcIndex = ProcId; } }; @@ -1413,16 +1409,11 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef, } static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants, - ArrayRef<unsigned> ProcIndices) { + unsigned ProcId) { std::vector<Record *> Preds; for (auto &Variant : Variants) { if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar")) continue; - - if (ProcIndices[0] && Variant.ProcIdx) - if (!llvm::count(ProcIndices, Variant.ProcIdx)) - continue; - Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate")); } return Preds; @@ -1444,12 +1435,14 @@ void PredTransitions::getIntersectingVariants( Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel"); VarProcIdx = SchedModels.getProcModel(ModelDef).Index; } - // Push each variant. Assign TransVecIdx later. - const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants"); - for (Record *VarDef : VarDefs) - Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0); - if (VarProcIdx == 0) - GenericRW = true; + if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) { + // Push each variant. Assign TransVecIdx later. + const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants"); + for (Record *VarDef : VarDefs) + Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0); + if (VarProcIdx == 0) + GenericRW = true; + } } for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end(); AI != AE; ++AI) { @@ -1461,6 +1454,17 @@ void PredTransitions::getIntersectingVariants( Record *ModelDef = (*AI)->getValueAsDef("SchedModel"); AliasProcIdx = SchedModels.getProcModel(ModelDef).Index; } + if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex) + continue; + if (!Variants.empty()) { + const CodeGenProcModel &PM = + *(SchedModels.procModelBegin() + AliasProcIdx); + PrintFatalError((*AI)->getLoc(), + "Multiple variants defined for processor " + + PM.ModelName + + " Ensure only one SchedAlias exists per RW."); + } + const CodeGenSchedRW &AliasRW = SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW")); @@ -1475,25 +1479,10 @@ void PredTransitions::getIntersectingVariants( GenericRW = true; } std::vector<Record *> AllPreds = - getAllPredicates(Variants, TransVec[TransIdx].ProcIndices); + getAllPredicates(Variants, TransVec[TransIdx].ProcIndex); for (TransVariant &Variant : Variants) { // Don't expand variants if the processor models don't intersect. // A zero processor index means any processor. - SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices; - if (ProcIndices[0] && Variant.ProcIdx) { - unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(), - Variant.ProcIdx); - if (!Cnt) - continue; - if (Cnt > 1) { - const CodeGenProcModel &PM = - *(SchedModels.procModelBegin() + Variant.ProcIdx); - PrintFatalError(Variant.VarOrSeqDef->getLoc(), - "Multiple variants defined for processor " + - PM.ModelName + - " Ensure only one SchedAlias exists per RW."); - } - } if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) { Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate"); if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm)) @@ -1526,9 +1515,6 @@ pushVariant(const TransVariant &VInfo, bool IsRead) { // If this operand transition is reached through a processor-specific alias, // then the whole transition is specific to this processor. - if (VInfo.ProcIdx != 0) - Trans.ProcIndices.assign(1, VInfo.ProcIdx); - IdxVec SelectedRWs; if (VInfo.VarOrSeqDef->isSubClassOf("SchedVar")) { Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate"); @@ -1632,9 +1618,9 @@ bool PredTransitions::substituteVariants(const PredTransition &Trans) { // PredTransitions. Remember the first new transition. unsigned StartIdx = TransVec.size(); bool Subst = false; - TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndices); + assert(Trans.ProcIndex != 0); + TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndex); - assert(!llvm::count(Trans.ProcIndices, 0)); // Visit each original write sequence. for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator WSI = Trans.WriteSequences.begin(), WSE = Trans.WriteSequences.end(); @@ -1683,8 +1669,8 @@ static void dumpTransition(const CodeGenSchedModels &SchedModels, << FromSC.Index << ") to " << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "(" << SCTrans.ToClassIdx << ") on pred term: ("; - dumpRecVec(Preds); dbgs() << ") on processor indices: ("; - dumpIdxVec(SCTrans.ProcIndices); dbgs() << ")\n"); + dumpRecVec(Preds); + dbgs() << ") on processor (" << SCTrans.ProcIndex << ")\n"); } // Create a new SchedClass for each variant found by inferFromRW. Pass static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions, @@ -1706,15 +1692,12 @@ static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions, // Transition should not contain processor indices already assigned to // InstRWs in this scheduling class. const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx); - llvm::copy_if(I->ProcIndices, std::back_inserter(SCTrans.ProcIndices), - [&FromSC](unsigned PIdx) { - return !FromSC.InstRWProcIndices.count(PIdx); - }); - if (SCTrans.ProcIndices.empty()) + if (FromSC.InstRWProcIndices.count(I->ProcIndex)) continue; + SCTrans.ProcIndex = I->ProcIndex; SCTrans.ToClassIdx = SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant, - OperReadsVariant, I->ProcIndices); + OperReadsVariant, I->ProcIndex); // The final PredTerm is unique set of predicates guarding the transition. RecVec Preds; @@ -1745,7 +1728,7 @@ makePerProcessorTransitions(const PredTransition &Trans, for (unsigned ProcId : ProcIndices) { assert(ProcId != 0); PerCpuTransVec.push_back(Trans); - PerCpuTransVec.back().ProcIndices.assign(1, ProcId); + PerCpuTransVec.back().ProcIndex = ProcId; } return PerCpuTransVec; } @@ -1763,8 +1746,6 @@ void CodeGenSchedModels::inferFromRW(ArrayRef<unsigned> OperWrites, // of SchedWrites for the current SchedClass. std::vector<PredTransition> LastTransitions; LastTransitions.emplace_back(); - LastTransitions.back().ProcIndices.append(ProcIndices.begin(), - ProcIndices.end()); for (unsigned WriteIdx : OperWrites) { IdxVec WriteSeq; @@ -2270,7 +2251,7 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const { if (!Transitions.empty()) { dbgs() << "\n Transitions for Proc "; for (const CodeGenSchedTransition &Transition : Transitions) { - dumpIdxVec(Transition.ProcIndices); + dbgs() << Transition.ProcIndex << ", "; } } dbgs() << '\n'; diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h index 311adafdf977..3fa642607b63 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.h +++ b/llvm/utils/TableGen/CodeGenSchedule.h @@ -96,7 +96,7 @@ struct CodeGenSchedRW { /// Represent a transition between SchedClasses induced by SchedVariant. struct CodeGenSchedTransition { unsigned ToClassIdx; - IdxVec ProcIndices; + unsigned ProcIndex; RecVec PredTerm; }; diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index df7faed8aea5..9cb25af28018 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -1007,8 +1007,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, bool HasVariants = false; for (const CodeGenSchedTransition &CGT : make_range(SC.Transitions.begin(), SC.Transitions.end())) { - if (CGT.ProcIndices[0] == 0 || - is_contained(CGT.ProcIndices, ProcModel.Index)) { + if (CGT.ProcIndex == ProcModel.Index) { HasVariants = true; break; } @@ -1551,9 +1550,8 @@ static void collectProcessorIndices(const CodeGenSchedClass &SC, // transition rules specified by variant class `SC`. for (const CodeGenSchedTransition &T : SC.Transitions) { IdxVec PI; - std::set_union(T.ProcIndices.begin(), T.ProcIndices.end(), - ProcIndices.begin(), ProcIndices.end(), - std::back_inserter(PI)); + std::set_union(&T.ProcIndex, &T.ProcIndex + 1, ProcIndices.begin(), + ProcIndices.end(), std::back_inserter(PI)); ProcIndices.swap(PI); } } @@ -1607,7 +1605,7 @@ void SubtargetEmitter::emitSchedModelHelpersImpl( // Now emit transitions associated with processor PI. const CodeGenSchedTransition *FinalT = nullptr; for (const CodeGenSchedTransition &T : SC.Transitions) { - if (PI != 0 && !count(T.ProcIndices, PI)) + if (PI != 0 && T.ProcIndex != PI) continue; // Emit only transitions based on MCSchedPredicate, if it's the case. _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
