Author: Florian Hahn Date: 2020-12-08T21:11:33Z New Revision: 4c69b1b98a9aeda363c7126a0cfa6e2e88e593c5
URL: https://github.com/llvm/llvm-project/commit/4c69b1b98a9aeda363c7126a0cfa6e2e88e593c5 DIFF: https://github.com/llvm/llvm-project/commit/4c69b1b98a9aeda363c7126a0cfa6e2e88e593c5.diff LOG: [AArch64] Fix rottype use in complex instr defs. It seems like the order here is wrong. Types like i32 do not take any arguments. Currently this is not a problem, because the patterns are not actually used with any nodes, but will fail once it is used with real ISD nodes. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D91345 Added: Modified: llvm/lib/Target/AArch64/AArch64InstrFormats.td Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 68dc477567a5..6d17b283231a 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -10603,14 +10603,14 @@ multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype, [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; def v8f16 : BaseSIMDThreeSameVectorComplex<1, U, 0b01, opcode, V128, rottype, asm, ".8h", [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; } let Predicates = [HasComplxNum, HasNEON] in { @@ -10619,21 +10619,21 @@ multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype, [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; def v4f32 : BaseSIMDThreeSameVectorComplex<1, U, 0b10, opcode, V128, rottype, asm, ".4s", [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; def v2f64 : BaseSIMDThreeSameVectorComplex<1, U, 0b11, opcode, V128, rottype, asm, ".2d", [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; } } @@ -10675,14 +10675,14 @@ multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode, [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; def v8f16 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b01, opcode, V128, rottype, asm, ".8h", [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; } let Predicates = [HasComplxNum, HasNEON] in { @@ -10691,21 +10691,21 @@ multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode, [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; def v4f32 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b10, opcode, V128, rottype, asm, ".4s", [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; def v2f64 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b11, opcode, V128, rottype, asm, ".2d", [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm), - (rottype i32:$rot)))]>; + (i32 rottype:$rot)))]>; } } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
