Author: Craig Topper Date: 2020-12-14T17:22:55-08:00 New Revision: b094eaa392322a9a0073c84f0b6ea320d80dafcf
URL: https://github.com/llvm/llvm-project/commit/b094eaa392322a9a0073c84f0b6ea320d80dafcf DIFF: https://github.com/llvm/llvm-project/commit/b094eaa392322a9a0073c84f0b6ea320d80dafcf.diff LOG: [RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0 destination. Added: Modified: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/test/MC/RISCV/rvv/invalid.s Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index fbc67e4c4195..3225559f6c4d 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2306,7 +2306,9 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst, unsigned Opcode = Inst.getOpcode(); if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM || Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || - Opcode == RISCV::VSBC_VXM) + Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM || + Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM || + Opcode == RISCV::VMERGE_VXM) return Error(Loc, "The destination vector register group cannot be V0."); // Regardless masked or unmasked version, the number of operands is the diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s index 671373050441..b741cce7abd7 100644 --- a/llvm/test/MC/RISCV/rvv/invalid.s +++ b/llvm/test/MC/RISCV/rvv/invalid.s @@ -616,3 +616,19 @@ vmsge.vx v0, v4, a0, v0.t vmsge.vx v8, v4, a0, v0.t, v2 # CHECK-ERROR: invalid operand for instruction # CHECK-ERROR-LABEL: vmsge.vx v8, v4, a0, v0.t, v2 + +vmerge.vim v0, v1, 1, v0 +# CHECK-ERROR: The destination vector register group cannot be V0. +# CHECK-ERROR-LABEL: vmerge.vim v0, v1, 1, v0 + +vmerge.vvm v0, v1, v2, v0 +# CHECK-ERROR: The destination vector register group cannot be V0. +# CHECK-ERROR-LABEL: vmerge.vvm v0, v1, v2, v0 + +vmerge.vxm v0, v1, x1, v0 +# CHECK-ERROR: The destination vector register group cannot be V0. +# CHECK-ERROR-LABEL: vmerge.vxm v0, v1, x1, v0 + +vfmerge.vfm v0, v1, f1, v0 +# CHECK-ERROR: The destination vector register group cannot be V0. +# CHECK-ERROR-LABEL: vfmerge.vfm v0, v1, f1, v0 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
