Author: Paul Walker Date: 2020-12-15T16:10:38Z New Revision: 632f4d2747f0777157d10456dd431d8f4cece845
URL: https://github.com/llvm/llvm-project/commit/632f4d2747f0777157d10456dd431d8f4cece845 DIFF: https://github.com/llvm/llvm-project/commit/632f4d2747f0777157d10456dd431d8f4cece845.diff LOG: [NFC] Fix a few SVEInstrInfo related stylistic issues. Added: Modified: llvm/lib/Target/AArch64/AArch64.td llvm/lib/Target/AArch64/AArch64InstrFormats.td llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td llvm/lib/Target/AArch64/SVEInstrFormats.td Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 41abfa32da62f..5bafe430a1b4c 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -437,7 +437,6 @@ def HasV8_5aOps : SubtargetFeature< def HasV8_6aOps : SubtargetFeature< "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", - [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 6d17b283231a2..8e01a8cf7beb9 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -325,7 +325,7 @@ def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { } def SImm8Operand : SImmOperand<8>; -def simm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 127; }]> { +def simm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> { let ParserMatchClass = SImm8Operand; let DecoderMethod = "DecodeSImm<8>"; } diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 22f78ce61128f..86cfdf8f7cf97 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -558,11 +558,11 @@ void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, StackOffset Off = StackOffset::getFixed(Offset); unsigned i = 0; - while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } + const MachineFunction *MF = MI.getParent()->getParent(); const AArch64InstrInfo *TII = MF->getSubtarget<AArch64Subtarget>().getInstrInfo(); @@ -604,7 +604,6 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, const AArch64InstrInfo *TII = MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); const AArch64FrameLowering *TFI = getFrameLowering(MF); - int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); bool Tagged = MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index bdf5d1d771c79..adbace24ee6c5 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -575,7 +575,7 @@ let Predicates = [HasSVE] in { } // Select elements from either vector (predicated) - defm SEL_ZPZZ : sve_int_sel_vvv<"sel", vselect>; + defm SEL_ZPZZ : sve_int_sel_vvv<"sel", vselect>; defm SPLICE_ZPZ : sve_int_perm_splice<"splice", int_aarch64_sve_splice>; @@ -1062,7 +1062,7 @@ let Predicates = [HasSVE] in { def PRFS_PRR : sve_mem_prfm_ss<0b101, "prfw", GPR64NoXZRshifted32>; def PRFD_PRR : sve_mem_prfm_ss<0b111, "prfd", GPR64NoXZRshifted64>; -multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instruction RegImmInst, Instruction RegRegInst, int scale, ComplexPattern AddrCP> { + multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instruction RegImmInst, Instruction RegRegInst, int scale, ComplexPattern AddrCP> { // reg + imm let AddedComplexity = 2 in { def _reg_imm : Pat<(prefetch (PredTy PPR_3b:$gp), (am_sve_indexed_s6 GPR64sp:$base, simm6s1:$offset), (i32 sve_prfop:$prfop)), @@ -1735,7 +1735,6 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio def : Pat<(nxv2f64 (bitconvert (nxv2i64 ZPR:$src))), (nxv2f64 ZPR:$src)>; def : Pat<(nxv2f64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2f64 ZPR:$src)>; def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>; - } let Predicates = [IsLE, HasBF16, HasSVE] in { @@ -2434,6 +2433,7 @@ let Predicates = [HasSVE2] in { (UMULH_ZZZ_S $Op1, $Op2)>; def : Pat<(nxv2i64 (int_aarch64_sve_umulh (nxv2i1 (AArch64ptrue 31)), nxv2i64:$Op1, nxv2i64:$Op2)), (UMULH_ZZZ_D $Op1, $Op2)>; + // SVE2 complex integer dot product (indexed) defm CDOT_ZZZI : sve2_cintx_dot_by_indexed_elem<"cdot", int_aarch64_sve_cdot_lane>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index c86b425422580..0db00247cd01b 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1012,8 +1012,8 @@ multiclass sve_int_perm_dup_i<string asm> { (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>; } -class sve_int_perm_tbl<bits<2> sz8_64, bits<2> opc, string asm, - ZPRRegOp zprty, RegisterOperand VecList> +class sve_int_perm_tbl<bits<2> sz8_64, bits<2> opc, string asm, ZPRRegOp zprty, + RegisterOperand VecList> : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", @@ -1422,7 +1422,6 @@ multiclass sve_int_pred_log<bits<4> opc, string asm, SDPatternOperator op, !cast<Instruction>(NAME), PTRUE_D>; } - //===----------------------------------------------------------------------===// // SVE Logical Mask Immediate Group //===----------------------------------------------------------------------===// @@ -1675,7 +1674,6 @@ multiclass sve_fp_ftmad<string asm, SDPatternOperator op> { (!cast<Instruction>(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, imm32_0_7:$imm)>; } - //===----------------------------------------------------------------------===// // SVE Floating Point Arithmetic - Unpredicated Group //===----------------------------------------------------------------------===// @@ -2102,7 +2100,8 @@ class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm, let ElementSize = zprty.ElementSize; } -multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm, SDPatternOperator op> { +multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm, + SDPatternOperator op> { def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>; def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>; def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>; @@ -2262,7 +2261,7 @@ multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm, //===----------------------------------------------------------------------===// class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype, - RegisterOperand o_zprtype, ElementSizeEnum size> + RegisterOperand o_zprtype, ElementSizeEnum Sz> : I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn), asm, "\t$Zd, $Pg/m, $Zn", "", @@ -2281,7 +2280,7 @@ class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype, let Constraints = "$Zd = $_Zd"; let DestructiveInstType = DestructiveOther; - let ElementSize = size; + let ElementSize = Sz; } multiclass sve_fp_2op_p_zd<bits<7> opc, string asm, @@ -2691,7 +2690,8 @@ multiclass sve2_int_mla_by_indexed_elem<bits<2> opc, bit S, string asm, // SVE2 Integer Multiply-Add Long - Indexed Group //===----------------------------------------------------------------------===// -multiclass sve2_int_mla_long_by_indexed_elem<bits<4> opc, string asm, SDPatternOperator op> { +multiclass sve2_int_mla_long_by_indexed_elem<bits<4> opc, string asm, + SDPatternOperator op> { def _S : sve2_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} }, asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH32b> { bits<3> Zm; @@ -3510,7 +3510,8 @@ multiclass sve2_int_abs diff _accum_long<bits<2> opc, string asm, def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _D)>; } -multiclass sve2_int_addsub_long_carry<bits<2> opc, string asm, SDPatternOperator op> { +multiclass sve2_int_addsub_long_carry<bits<2> opc, string asm, + SDPatternOperator op> { def _S : sve2_int_abs diff _accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm, ZPR32, ZPR32>; def _D : sve2_int_abs diff _accum<{ opc{1}, 0b1 }, { 0b010, opc{0} }, asm, @@ -3554,7 +3555,7 @@ multiclass sve2_int_bin_shift_imm_right_narrow_bottom<bits<3> opc, string asm, let Inst{19} = imm{3}; } def _S : sve2_int_bin_shift_imm_narrow_bottom<{1,?,?}, opc, asm, ZPR32, ZPR64, - vecshiftR32> { + tvecshiftR32> { let Inst{20-19} = imm{4-3}; } def : SVE_2_Op_Imm_Pat<nxv16i8, op, nxv8i16, i32, tvecshiftR8, !cast<Instruction>(NAME # _B)>; @@ -3594,7 +3595,7 @@ multiclass sve2_int_bin_shift_imm_right_narrow_top<bits<3> opc, string asm, let Inst{19} = imm{3}; } def _S : sve2_int_bin_shift_imm_narrow_top<{1,?,?}, opc, asm, ZPR32, ZPR64, - vecshiftR32> { + tvecshiftR32> { let Inst{20-19} = imm{4-3}; } def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv8i16, i32, tvecshiftR8, !cast<Instruction>(NAME # _B)>; @@ -4112,6 +4113,7 @@ multiclass sve2_int_rotate_right_imm<string asm, SDPatternOperator op> { let Inst{22} = imm{5}; let Inst{20-19} = imm{4-3}; } + def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv16i8, i32, tvecshiftR8, !cast<Instruction>(NAME # _B)>; def : SVE_3_Op_Imm_Pat<nxv8i16, op, nxv8i16, nxv8i16, i32, tvecshiftR16, !cast<Instruction>(NAME # _H)>; def : SVE_3_Op_Imm_Pat<nxv4i32, op, nxv4i32, nxv4i32, i32, tvecshiftR32, !cast<Instruction>(NAME # _S)>; @@ -4445,8 +4447,7 @@ class sve_int_cterm<bit sz, bit opc, string asm, RegisterClass rt> } class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm, - RegisterClass gprty, PPRRegOp pprty, - ValueType vt, SDPatternOperator op> + RegisterClass gprty, PPRRegOp pprty> : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm), asm, "\t$Pd, $Rn, $Rm", "", []>, Sched<[]> { @@ -4467,27 +4468,27 @@ class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm, } multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op> { - def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8, nxv16i1, op>; - def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16, nxv8i1, op>; - def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32, nxv4i1, op>; - def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64, nxv2i1, op>; + def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8>; + def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16>; + def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32>; + def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64>; def : SVE_2_Op_Pat<nxv16i1, op, i32, i32, !cast<Instruction>(NAME # _B)>; - def : SVE_2_Op_Pat<nxv8i1, op, i32, i32, !cast<Instruction>(NAME # _H)>; - def : SVE_2_Op_Pat<nxv4i1, op, i32, i32, !cast<Instruction>(NAME # _S)>; - def : SVE_2_Op_Pat<nxv2i1, op, i32, i32, !cast<Instruction>(NAME # _D)>; + def : SVE_2_Op_Pat<nxv8i1, op, i32, i32, !cast<Instruction>(NAME # _H)>; + def : SVE_2_Op_Pat<nxv4i1, op, i32, i32, !cast<Instruction>(NAME # _S)>; + def : SVE_2_Op_Pat<nxv2i1, op, i32, i32, !cast<Instruction>(NAME # _D)>; } multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op> { - def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8, nxv16i1, op>; - def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16, nxv8i1, op>; - def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32, nxv4i1, op>; - def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64, nxv2i1, op>; + def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>; + def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>; + def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>; + def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; def : SVE_2_Op_Pat<nxv16i1, op, i64, i64, !cast<Instruction>(NAME # _B)>; - def : SVE_2_Op_Pat<nxv8i1, op, i64, i64, !cast<Instruction>(NAME # _H)>; - def : SVE_2_Op_Pat<nxv4i1, op, i64, i64, !cast<Instruction>(NAME # _S)>; - def : SVE_2_Op_Pat<nxv2i1, op, i64, i64, !cast<Instruction>(NAME # _D)>; + def : SVE_2_Op_Pat<nxv8i1, op, i64, i64, !cast<Instruction>(NAME # _H)>; + def : SVE_2_Op_Pat<nxv4i1, op, i64, i64, !cast<Instruction>(NAME # _S)>; + def : SVE_2_Op_Pat<nxv2i1, op, i64, i64, !cast<Instruction>(NAME # _D)>; } class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm, @@ -4520,7 +4521,6 @@ multiclass sve2_int_while_rr<bits<1> rw, string asm, string op> { def : SVE_2_Op_Pat<nxv8i1, !cast<SDPatternOperator>(op # _h), i64, i64, !cast<Instruction>(NAME # _H)>; def : SVE_2_Op_Pat<nxv4i1, !cast<SDPatternOperator>(op # _s), i64, i64, !cast<Instruction>(NAME # _S)>; def : SVE_2_Op_Pat<nxv2i1, !cast<SDPatternOperator>(op # _d), i64, i64, !cast<Instruction>(NAME # _D)>; - } //===----------------------------------------------------------------------===// @@ -4814,10 +4814,11 @@ multiclass sve_int_index_rr<string asm, SDPatternOperator op> { def : SVE_2_Op_Pat<nxv4i32, op, i32, i32, !cast<Instruction>(NAME # _S)>; def : SVE_2_Op_Pat<nxv2i64, op, i64, i64, !cast<Instruction>(NAME # _D)>; } -// + //===----------------------------------------------------------------------===// // SVE Bitwise Shift - Predicated Group //===----------------------------------------------------------------------===// + class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm, ZPRRegOp zprty, Operand immtype> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), @@ -5087,6 +5088,7 @@ multiclass sve_int_bin_cons_shift_imm_right<bits<2> opc, string asm, def : SVE_Shift_DupImm_All_Active_Pat<nxv4i32, op, nxv4i1, i32, SVEShiftImmR32, !cast<Instruction>(NAME # _S)>; def : SVE_Shift_DupImm_All_Active_Pat<nxv2i64, op, nxv2i1, i64, SVEShiftImmR64, !cast<Instruction>(NAME # _D)>; } + //===----------------------------------------------------------------------===// // SVE Memory - Store Group //===----------------------------------------------------------------------===// @@ -5595,8 +5597,7 @@ class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm, PPRRegOp pprty> : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm), asm, "\t$Pd, $Pn, $Pm", - "", - []>, Sched<[]> { + "", []>, Sched<[]> { bits<4> Pd; bits<4> Pm; bits<4> Pn; @@ -6139,7 +6140,6 @@ multiclass sve_int_perm_compact<string asm, SDPatternOperator op> { def : SVE_2_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>; } - //===----------------------------------------------------------------------===// // SVE Memory - Contiguous Load Group //===----------------------------------------------------------------------===// @@ -7051,7 +7051,6 @@ multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm, } - class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), asm, "\t$prfop, $Pg, [$Zn, $imm5]", @@ -7135,7 +7134,6 @@ multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> { def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>; } - //===----------------------------------------------------------------------===// // SVE Integer Misc - Unpredicated Group //===----------------------------------------------------------------------===// @@ -7872,8 +7870,8 @@ multiclass sve_mem_ldor_ss<bits<2> sz, string asm, RegisterOperand listty, def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; - def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$gp), (AddrCP GPR64sp:$base, gprty:$offset))), - (!cast<Instruction>(NAME) PPR3bAny:$gp, GPR64sp:$base, gprty:$offset)>; + def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$gp), (AddrCP GPR64sp:$base, gprty:$offset))), + (!cast<Instruction>(NAME) PPR3bAny:$gp, GPR64sp:$base, gprty:$offset)>; } //===----------------------------------------------------------------------===// _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
