Author: Craig Topper Date: 2020-12-15T13:54:41-08:00 New Revision: 028efac2d7c2a32c35a093e53ea12f527edff7c7
URL: https://github.com/llvm/llvm-project/commit/028efac2d7c2a32c35a093e53ea12f527edff7c7 DIFF: https://github.com/llvm/llvm-project/commit/028efac2d7c2a32c35a093e53ea12f527edff7c7.diff LOG: [RISCV] Only custom legalize i32 arguments to vector intrinsics on RV64. Added: Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 529a5bf784f4..c0202e3f19e0 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -340,9 +340,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, if (Subtarget.hasStdExtV()) { setBooleanVectorContents(ZeroOrOneBooleanContent); + // RVV intrinsics may have illegal operands. - for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) - setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom); + if (Subtarget.is64Bit()) + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom); } // Function alignments. _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
