Author: Fraser Cormack Date: 2020-12-28T07:11:10Z New Revision: d85a198e85253b6b39d9b86eb7afd3332637bcbe
URL: https://github.com/llvm/llvm-project/commit/d85a198e85253b6b39d9b86eb7afd3332637bcbe DIFF: https://github.com/llvm/llvm-project/commit/d85a198e85253b6b39d9b86eb7afd3332637bcbe.diff LOG: [RISCV] Pattern-match more vector-splatted constants This patch extends the pattern-matching capability of vector-splatted constants. When illegally-typed constants are legalized they are canonically sign-extended to XLenVT. This preserves the sign and allows us to match simm5. If they were zero-extended for whatever reason we'd lose that ability: e.g. `(i8 -1) -> (XLenVT 255)` would not be matched under the current logic. To address this we first manually sign-extend the splatted constant from the vector element type to int64_t. This preserves the semantics while removing any implicitly-truncated bits. The corresponding logic for uimm5 was not updated, the rationale being that neither sign- nor zero-extending a legal uimm5 immediate should change that (unless we expect actual "garbage" upper bits). Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D93837 Added: Modified: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 0d58a4a7e03c..2a815863a81c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -448,16 +448,25 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) { int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue(); - // TODO: First truncate the constant to the vector element type since the - // bits will be implicitly truncated anyway. This would catch cases where the - // immediate was zero-extended instead of sign-extended: we would still want - // to match (i8 -1) -> (XLenVT 255) as a simm5, for example + // Both ISD::SPLAT_VECTOR and RISCVISD::SPLAT_VECTOR_I64 share semantics when + // the operand type is wider than the resulting vector element type: an + // implicit truncation first takes place. Therefore, perform a manual + // truncation/sign-extension in order to ignore any truncated bits and catch + // any zero-extended immediate. + // For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first + // sign-extending to (XLenVT -1). + auto XLenVT = Subtarget->getXLenVT(); + assert(XLenVT == N.getOperand(0).getSimpleValueType() && + "Unexpected splat operand type"); + auto EltVT = N.getValueType().getVectorElementType(); + if (EltVT.bitsLT(XLenVT)) { + SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits()); + } + if (!isInt<5>(SplatImm)) return false; - SplatVal = - CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT()); - + SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), XLenVT); return true; } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
