Author: Kazushi (Jam) Marukawa Date: 2021-01-04T18:19:18+09:00 New Revision: 74e7cb26b9a3ff3f64883cc2418d9916b5e9257d
URL: https://github.com/llvm/llvm-project/commit/74e7cb26b9a3ff3f64883cc2418d9916b5e9257d DIFF: https://github.com/llvm/llvm-project/commit/74e7cb26b9a3ff3f64883cc2418d9916b5e9257d.diff LOG: [VE] Remove VA.needsCustom checks Remove VA.needsCustom checks which are copied from Sparc implementation at the very beginning of VE implementation. Add assert to sanity-check VA.needsCustom flag, also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93847 Added: Modified: llvm/lib/Target/VE/VEISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index ea9281a00502..5a3a9f504e30 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -314,6 +314,7 @@ VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; assert(VA.isRegLoc() && "Can only return in registers!"); + assert(!VA.needsCustom() && "Unexpected custom lowering"); SDValue OutVal = OutVals[i]; // Integer return values must be sign or zero extended by the callee. @@ -349,8 +350,6 @@ VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, llvm_unreachable("Unknown loc info!"); } - assert(!VA.needsCustom() && "Unexpected custom lowering"); - Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); // Guarantee that all emitted copies are stuck together with flags. @@ -390,6 +389,7 @@ SDValue VETargetLowering::LowerFormalArguments( for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; + assert(!VA.needsCustom() && "Unexpected custom lowering"); if (VA.isRegLoc()) { // This argument is passed in a register. // All integer register arguments are promoted by the caller to i64. @@ -399,11 +399,6 @@ SDValue VETargetLowering::LowerFormalArguments( MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); - // Get the high bits for i32 struct elements. - if (VA.getValVT() == MVT::i32 && VA.needsCustom()) - Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, - DAG.getConstant(32, DL, MVT::i32)); - // The caller promoted the argument, so insert an Assert?ext SDNode so we // won't promote the value again in this function. switch (VA.getLocInfo()) { @@ -734,6 +729,7 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; + assert(!VA.needsCustom() && "Unexpected custom lowering"); unsigned Reg = VA.getLocReg(); // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can @@ -751,11 +747,6 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, InGlue = Chain.getValue(2); } - // Get the high bits for i32 struct elements. - if (VA.getValVT() == MVT::i32 && VA.needsCustom()) - RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, - DAG.getConstant(32, DL, MVT::i32)); - // The callee promoted the return value, so insert an Assert?ext SDNode so // we won't promote the value again in this function. switch (VA.getLocInfo()) { _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
