Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 83a93ae63b1c8cc515a08c7fc4b78813e448c874
URL: https://github.com/llvm/llvm-project/commit/83a93ae63b1c8cc515a08c7fc4b78813e448c874 DIFF: https://github.com/llvm/llvm-project/commit/83a93ae63b1c8cc515a08c7fc4b78813e448c874.diff LOG: [RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94637 Added: llvm/test/MC/RISCV/rv32zba-invalid.s llvm/test/MC/RISCV/rv32zba-valid.s Modified: llvm/lib/Target/RISCV/RISCVInstrInfoB.td llvm/test/MC/RISCV/rv64zba-invalid.s llvm/test/MC/RISCV/rv64zba-valid.s Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index 537fbf9a7676..ef0a29d40893 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -224,6 +224,12 @@ def ORN : ALU_rr<0b0100000, 0b110, "orn">, Sched<[]>; def XNOR : ALU_rr<0b0100000, 0b100, "xnor">, Sched<[]>; } // Predicates = [HasStdExtZbbOrZbp] +let Predicates = [HasStdExtZba] in { +def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">, Sched<[]>; +def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">, Sched<[]>; +def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">, Sched<[]>; +} // Predicates = [HasStdExtZba] + let Predicates = [HasStdExtZbb] in { def SLO : ALU_rr<0b0010000, 0b001, "slo">, Sched<[]>; def SRO : ALU_rr<0b0010000, 0b101, "sro">, Sched<[]>; @@ -372,6 +378,9 @@ def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>; let Predicates = [HasStdExtZba, IsRV64] in { def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>; def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">, Sched<[]>; +def SH1ADDUW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">, Sched<[]>; +def SH2ADDUW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">, Sched<[]>; +def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">, Sched<[]>; } // Predicates = [HasStdExtZbb, IsRV64] let Predicates = [HasStdExtZbb, IsRV64] in { diff --git a/llvm/test/MC/RISCV/rv32zba-invalid.s b/llvm/test/MC/RISCV/rv32zba-invalid.s new file mode 100644 index 000000000000..64adfe03fdfb --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zba-invalid.s @@ -0,0 +1,8 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zba < %s 2>&1 | FileCheck %s + +# Too few operands +sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sh2add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sh3add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32zba-valid.s b/llvm/test/MC/RISCV/rv32zba-valid.s new file mode 100644 index 000000000000..20f40d8d44da --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zba-valid.s @@ -0,0 +1,23 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ +# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# With Bitmanip base extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zba -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zba < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zba -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sh1add t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x20] +sh1add t0, t1, t2 +# CHECK-ASM-AND-OBJ: sh2add t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x20] +sh2add t0, t1, t2 +# CHECK-ASM-AND-OBJ: sh3add t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x20] +sh3add t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64zba-invalid.s b/llvm/test/MC/RISCV/rv64zba-invalid.s index 28f04e33fc0d..02ba66d87949 100644 --- a/llvm/test/MC/RISCV/rv64zba-invalid.s +++ b/llvm/test/MC/RISCV/rv64zba-invalid.s @@ -7,3 +7,9 @@ slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer i slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63] # Too few operands add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sh1add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sh2add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sh3add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64zba-valid.s b/llvm/test/MC/RISCV/rv64zba-valid.s index 7928f201cd08..9cce642cb298 100644 --- a/llvm/test/MC/RISCV/rv64zba-valid.s +++ b/llvm/test/MC/RISCV/rv64zba-valid.s @@ -18,3 +18,12 @@ slli.uw t0, t1, 0 # CHECK-ASM-AND-OBJ: add.uw t0, t1, t2 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08] add.uw t0, t1, t2 +# CHECK-ASM-AND-OBJ: sh1add.uw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x20] +sh1add.uw t0, t1, t2 +# CHECK-ASM-AND-OBJ: sh2add.uw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x20] +sh2add.uw t0, t1, t2 +# CHECK-ASM-AND-OBJ: sh3add.uw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x20] +sh3add.uw t0, t1, t2 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
