Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff
URL: https://github.com/llvm/llvm-project/commit/f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff DIFF: https://github.com/llvm/llvm-project/commit/f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff.diff LOG: [RISCV] Add xperm.* instructions to Zbp extension. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94999 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoB.td llvm/test/MC/RISCV/rv32zbp-invalid.s llvm/test/MC/RISCV/rv32zbp-valid.s llvm/test/MC/RISCV/rv64zbp-invalid.s llvm/test/MC/RISCV/rv64zbp-valid.s Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index 5a733c4bf771..37c64cc1631a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -252,6 +252,12 @@ def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>; def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>; } // Predicates = [HasStdExtZbp] +let Predicates = [HasStdExtZbp] in { +def XPERMN : ALU_rr<0b0010100, 0b010, "xperm.n">, Sched<[]>; +def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>; +def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>; +} // Predicates = [HasStdExtZbp] + let Predicates = [HasStdExtZbp] in { def SLOI : RVBShift_ri<0b00100, 0b001, OPC_OP_IMM, "sloi">, Sched<[]>; def SROI : RVBShift_ri<0b00100, 0b101, OPC_OP_IMM, "sroi">, Sched<[]>; @@ -405,6 +411,10 @@ def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>; def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>; } // Predicates = [HasStdExtZbp, IsRV64] +let Predicates = [HasStdExtZbp, IsRV64] in { +def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>; +} // Predicates = [HasStdExtZbp, IsRV64] + let Predicates = [HasStdExtZbp, IsRV64] in { def SLOIW : RVBShiftW_ri<0b0010000, 0b001, OPC_OP_IMM_32, "sloiw">, Sched<[]>; def SROIW : RVBShiftW_ri<0b0010000, 0b101, OPC_OP_IMM_32, "sroiw">, Sched<[]>; diff --git a/llvm/test/MC/RISCV/rv32zbp-invalid.s b/llvm/test/MC/RISCV/rv32zbp-invalid.s index de65a71bd0f6..f5eac72b3b88 100644 --- a/llvm/test/MC/RISCV/rv32zbp-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbp-invalid.s @@ -48,3 +48,9 @@ pack t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction packu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands packh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +xperm.n t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +xperm.b t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +xperm.h t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32zbp-valid.s b/llvm/test/MC/RISCV/rv32zbp-valid.s index 3ca28573addd..f05d72dc9ec2 100644 --- a/llvm/test/MC/RISCV/rv32zbp-valid.s +++ b/llvm/test/MC/RISCV/rv32zbp-valid.s @@ -78,3 +78,12 @@ orc.b t0, t1 # CHECK-OBJ: orc.b t0, t1 # CHECK-ASM: encoding: [0x93,0x52,0x73,0x28] gorci t0, t1, 7 +# CHECK-ASM-AND-OBJ: xperm.n t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28] +xperm.n t0, t1, t2 +# CHECK-ASM-AND-OBJ: xperm.b t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28] +xperm.b t0, t1, t2 +# CHECK-ASM-AND-OBJ: xperm.h t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28 +xperm.h t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64zbp-invalid.s b/llvm/test/MC/RISCV/rv64zbp-invalid.s index 8b98bdfa41b0..88adf2d47779 100644 --- a/llvm/test/MC/RISCV/rv64zbp-invalid.s +++ b/llvm/test/MC/RISCV/rv64zbp-invalid.s @@ -32,3 +32,5 @@ greviw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in shflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands unshflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +xperm.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64zbp-valid.s b/llvm/test/MC/RISCV/rv64zbp-valid.s index ec4e918173b3..7fbc684b9c3d 100644 --- a/llvm/test/MC/RISCV/rv64zbp-valid.s +++ b/llvm/test/MC/RISCV/rv64zbp-valid.s @@ -69,3 +69,6 @@ orc.b t0, t1 # CHECK-OBJ: orc.b t0, t1 # CHECK-ASM: encoding: [0x93,0x52,0x73,0x28] gorci t0, t1, 7 +# CHECK-ASM-AND-OBJ: xperm.w t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x02,0x73,0x28] +xperm.w t0, t1, t2 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
