Author: Kazu Hirata Date: 2021-01-22T23:25:05-08:00 New Revision: 49231c1f80803ae0f15963cce708cedf6e44088f
URL: https://github.com/llvm/llvm-project/commit/49231c1f80803ae0f15963cce708cedf6e44088f DIFF: https://github.com/llvm/llvm-project/commit/49231c1f80803ae0f15963cce708cedf6e44088f.diff LOG: [llvm] Use static_assert instead of assert (NFC) Identified with misc-static-assert. Added: Modified: llvm/include/llvm/IR/InstrTypes.h llvm/lib/Object/XCOFFObjectFile.cpp llvm/lib/Support/SHA1.cpp llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp llvm/lib/Target/X86/X86InsertPrefetch.cpp llvm/utils/TableGen/X86DisassemblerTables.cpp Removed: ################################################################################ diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h index 631665e3fc52e..7b99cc96b149b 100644 --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -802,8 +802,8 @@ class CmpInst : public Instruction { void setPredicate(Predicate P) { setSubclassData<PredicateField>(P); } static bool isFPPredicate(Predicate P) { - assert(FIRST_FCMP_PREDICATE == 0 && - "FIRST_FCMP_PREDICATE is required to be 0"); + static_assert(FIRST_FCMP_PREDICATE == 0, + "FIRST_FCMP_PREDICATE is required to be 0"); return P <= LAST_FCMP_PREDICATE; } diff --git a/llvm/lib/Object/XCOFFObjectFile.cpp b/llvm/lib/Object/XCOFFObjectFile.cpp index b0d772b6ff212..a16a458168d42 100644 --- a/llvm/lib/Object/XCOFFObjectFile.cpp +++ b/llvm/lib/Object/XCOFFObjectFile.cpp @@ -655,7 +655,8 @@ XCOFFObjectFile::relocations(const XCOFFSectionHeader32 &Sec) const { uint32_t NumRelocEntries = NumRelocEntriesOrErr.get(); - assert(sizeof(XCOFFRelocation32) == XCOFF::RelocationSerializationSize32); + static_assert( + sizeof(XCOFFRelocation32) == XCOFF::RelocationSerializationSize32, ""); auto RelocationOrErr = getObject<XCOFFRelocation32>(Data, reinterpret_cast<void *>(RelocAddr), NumRelocEntries * sizeof(XCOFFRelocation32)); diff --git a/llvm/lib/Support/SHA1.cpp b/llvm/lib/Support/SHA1.cpp index 417b13fea05a4..5dce44af9ecd8 100644 --- a/llvm/lib/Support/SHA1.cpp +++ b/llvm/lib/Support/SHA1.cpp @@ -225,7 +225,7 @@ void SHA1::update(ArrayRef<uint8_t> Data) { // Fast buffer filling for large inputs. while (Data.size() >= BLOCK_LENGTH) { assert(InternalState.BufferOffset == 0); - assert(BLOCK_LENGTH % 4 == 0); + static_assert(BLOCK_LENGTH % 4 == 0, ""); constexpr size_t BLOCK_LENGTH_32 = BLOCK_LENGTH / 4; for (size_t I = 0; I < BLOCK_LENGTH_32; ++I) InternalState.Buffer.L[I] = support::endian::read32be(&Data[I * 4]); diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 4a4aad02938a9..8061c6c509e08 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -1015,7 +1015,8 @@ MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) c : getVgprClassId(Width), Val - VGPR_MIN); } if (Val <= SGPR_MAX) { - assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. + // "SGPR_MIN <= Val" is always true and causes compilation warning. + static_assert(SGPR_MIN == 0, ""); return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); } @@ -1052,7 +1053,8 @@ MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) c assert(Width == OPW256 || Width == OPW512); if (Val <= SGPR_MAX) { - assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. + // "SGPR_MIN <= Val" is always true and causes compilation warning. + static_assert(SGPR_MIN == 0, ""); return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); } diff --git a/llvm/lib/Target/X86/X86InsertPrefetch.cpp b/llvm/lib/Target/X86/X86InsertPrefetch.cpp index 53925bbfd72fe..004e6fa5ebf4e 100644 --- a/llvm/lib/Target/X86/X86InsertPrefetch.cpp +++ b/llvm/lib/Target/X86/X86InsertPrefetch.cpp @@ -214,10 +214,10 @@ bool X86InsertPrefetch::runOnMachineFunction(MachineFunction &MF) { MF.CreateMachineInstr(Desc, Current->getDebugLoc(), true); MachineInstrBuilder MIB(MF, PFetch); - assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && - X86::AddrIndexReg == 2 && X86::AddrDisp == 3 && - X86::AddrSegmentReg == 4 && - "Unexpected change in X86 operand offset order."); + static_assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && + X86::AddrIndexReg == 2 && X86::AddrDisp == 3 && + X86::AddrSegmentReg == 4, + "Unexpected change in X86 operand offset order."); // This assumes X86::AddBaseReg = 0, {...}ScaleAmt = 1, etc. // FIXME(mtrofin): consider adding a: diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 76e4fd9a13eed..331664f875b7b 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -763,7 +763,7 @@ void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, } if (index == 256) { // If all 256 entries are MODRM_ONEENTRY, omit output. - assert(MODRM_ONEENTRY == 0); + static_assert(MODRM_ONEENTRY == 0, ""); --i2; o2 << "},\n"; } else { _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits