Author: Yunde Zhong Date: 2021-09-07T22:33:46-07:00 New Revision: 49dacda603b353662583664f302b8ece019a346c
URL: https://github.com/llvm/llvm-project/commit/49dacda603b353662583664f302b8ece019a346c DIFF: https://github.com/llvm/llvm-project/commit/49dacda603b353662583664f302b8ece019a346c.diff LOG: [tests] precommit tests for D107692 (cherry picked from commit 9790a2a72f60bb2caf891658c3c6a02b61e1f1a2) Added: llvm/test/CodeGen/AArch64/arm64-srl-and.ll Modified: Removed: ################################################################################ diff --git a/llvm/test/CodeGen/AArch64/arm64-srl-and.ll b/llvm/test/CodeGen/AArch64/arm64-srl-and.ll new file mode 100644 index 000000000000..2f024e444d25 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-srl-and.ll @@ -0,0 +1,29 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -O3 < %s | FileCheck %s + +; Disable the dagcombine if operand has multi use + +@g = global i16 0, align 4 +define i32 @srl_and() { +; CHECK-LABEL: srl_and: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: adrp x8, :got:g +; CHECK-NEXT: ldr x8, [x8, :got_lo12:g] +; CHECK-NEXT: mov w9, #50 +; CHECK-NEXT: ldrh w8, [x8] +; CHECK-NEXT: eor w8, w8, w9 +; CHECK-NEXT: sub w8, w8, #1 +; CHECK-NEXT: and w0, w8, w8, lsr #16 +; CHECK-NEXT: ret +entry: + %0 = load i16, i16* @g, align 4 + %1 = xor i16 %0, 50 + %tobool = icmp ne i16 %1, 0 + %lor.ext = zext i1 %tobool to i32 + %sub = add i16 %1, -1 + + %srl = zext i16 %sub to i32 + %and = and i32 %srl, %lor.ext + + ret i32 %and +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
