Author: Cullen Rhodes Date: 2021-09-08T20:47:08-07:00 New Revision: dc10ff25f54b64cbb36ac56769e01492c0315de8
URL: https://github.com/llvm/llvm-project/commit/dc10ff25f54b64cbb36ac56769e01492c0315de8 DIFF: https://github.com/llvm/llvm-project/commit/dc10ff25f54b64cbb36ac56769e01492c0315de8.diff LOG: [AArch64][SME] Fix imm bug in mov vector to tile aliases Also fixes a warning mentioned in D109359. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D109363 (cherry picked from commit 89786c2b992c3cb4c4a230542d2af34ec2915a08) Added: Modified: llvm/lib/Target/AArch64/SMEInstrFormats.td llvm/test/MC/AArch64/SME/mova-diagnostics.s Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 62089166f4b75..00fd374587bc2 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -480,7 +480,7 @@ multiclass sme_vector_to_tile_aliases<Instruction inst, MatrixTileVectorOperand tile_ty, ZPRRegOp zpr_ty, Operand imm_ty> { def : InstAlias<"mov\t$ZAd[$Rv, $imm], $Pg/m, $Zn", - (inst tile_ty:$ZAd, MatrixIndexGPR32Op12_15:$Rv, imm0_15:$imm, PPR3bAny:$Pg, zpr_ty:$Zn), 1>; + (inst tile_ty:$ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, zpr_ty:$Zn), 1>; } multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> { diff --git a/llvm/test/MC/AArch64/SME/mova-diagnostics.s b/llvm/test/MC/AArch64/SME/mova-diagnostics.s index 119a6b170af95..f09ec110f698a 100644 --- a/llvm/test/MC/AArch64/SME/mova-diagnostics.s +++ b/llvm/test/MC/AArch64/SME/mova-diagnostics.s @@ -158,6 +158,31 @@ mova z0.q, p0/m, za0h.q[w12, #0] // CHECK-NEXT: mova z0.q, p0/m, za0h.q[w12, #0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +mov z0.b, p0/m, za0h.b[w12, #16] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]. +// CHECK-NEXT: mov z0.b, p0/m, za0h.b[w12, #16] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov z0.h, p0/m, za0h.h[w12, #8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: mov z0.h, p0/m, za0h.h[w12, #8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov z0.s, p0/m, za0h.s[w12, #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3]. +// CHECK-NEXT: mov z0.s, p0/m, za0h.s[w12, #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov z0.d, p0/m, za0h.d[w12, #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1]. +// CHECK-NEXT: mov z0.d, p0/m, za0h.d[w12, #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov z0.q, p0/m, za0h.q[w12, #0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mov z0.q, p0/m, za0h.q[w12, #0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // vector-to-tile mova za0h.b[w12, #16], p0/m, z0.b @@ -185,6 +210,31 @@ mova za0h.q[w12, #0], p0/m, z0.q // CHECK-NEXT: mova za0h.q[w12, #0], p0/m, z0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +mov za0h.b[w12, #16], p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]. +// CHECK-NEXT: mov za0h.b[w12, #16], p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov za0h.h[w12, #8], p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: mov za0h.h[w12, #8], p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov za0h.s[w12, #4], p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3]. +// CHECK-NEXT: mov za0h.s[w12, #4], p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov za0h.d[w12, #2], p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1]. +// CHECK-NEXT: mov za0h.d[w12, #2], p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov za0h.q[w12, #0], p0/m, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mov za0h.q[w12, #0], p0/m, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // ------------------------------------------------------------------------- // // Invalid ZPR element width _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
