Author: Jessica Clarke Date: 2021-10-22T00:33:25-07:00 New Revision: 47f53eec648514daf87b9c0b1e1177bb8f7056ae
URL: https://github.com/llvm/llvm-project/commit/47f53eec648514daf87b9c0b1e1177bb8f7056ae DIFF: https://github.com/llvm/llvm-project/commit/47f53eec648514daf87b9c0b1e1177bb8f7056ae.diff LOG: [Mips] Add glue between CopyFromReg, CopyToReg and RDHWR nodes for TLS The MIPS ABI requires the thread pointer be accessed via rdhwr $3, $r29. This is currently represented by (CopyToReg $3, (RDHWR $29)) followed by a (CopyFromReg $3). However, there is no glue between these, meaning scheduling can break those apart. In particular, PR51691 is a report where PseudoSELECT_I was moved to between the CopyToReg and CopyFromReg, and since its expansion uses branches, it split the def and use of the physical register between two basic blocks, resulting in the def being eliminated and the use having no def. It also seems possible that a similar situation could arise splitting up the CopyToReg from the RDHWR, causing the RDHWR to use a destination register other than $3, violating the ABI requirement. Thus, add glue between all three nodes to ensure they aren't split up during instruction selection. No regression test is added since any test would be implictly relying on specific scheduling behaviour, so whilst it might be testing that glue is preventing reordering today, changes to scheduling behaviour could result in the test no longer being able to catch a regression here, as the reordering might no longer happen for other unrelated reasons. Fixes PR51691. Reviewed By: atanasyan, dim Differential Revision: https://reviews.llvm.org/D111967 (cherry picked from commit f5755c0849a56543ef6938352784fdd7b4596e4c) Added: Modified: llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp llvm/test/CodeGen/Mips/tls-static.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 7be5fc33a0aff..04a835f08855d 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -1027,12 +1027,13 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { } SDNode *Rdhwr = - CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0), + CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0), MVT::Glue, CurDAG->getRegister(Mips::HWR29, MVT::i32), CurDAG->getTargetConstant(0, DL, MVT::i32)); SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, - SDValue(Rdhwr, 0)); - SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT); + SDValue(Rdhwr, 0), SDValue(Rdhwr, 1)); + SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT, + Chain.getValue(1)); ReplaceNode(Node, ResNode.getNode()); return true; } diff --git a/llvm/test/CodeGen/Mips/tls-static.ll b/llvm/test/CodeGen/Mips/tls-static.ll index 85cbb9bcb15c1..584487c4c95f0 100644 --- a/llvm/test/CodeGen/Mips/tls-static.ll +++ b/llvm/test/CodeGen/Mips/tls-static.ll @@ -50,16 +50,16 @@ entry: ; STATIC32-LABEL: f2: ; STATIC32: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp) ; STATIC32: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) -; STATIC32: rdhwr $3, $29{{$}} ; STATIC32: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]]) +; STATIC32: rdhwr $3, $29{{$}} ; STATIC32: addu $[[R1:[0-9]+]], $3, $[[R0]] ; STATIC32: lw $2, 0($[[R1]]) ; STATIC64-LABEL: f2: ; STATIC64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2))) ; STATIC64: daddiu $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2))) -; STATIC64: rdhwr $3, $29{{$}} ; STATIC64: ld $[[R0:[0-9]+]], %gottprel(t2)($[[GP]]) +; STATIC64: rdhwr $3, $29{{$}} ; STATIC64: daddu $[[R1:[0-9]+]], $3, $[[R0]] ; STATIC64: lw $2, 0($[[R1]]) } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
