Author: Amara Emerson Date: 2022-07-29T15:21:57-07:00 New Revision: fc03fad3dde95d9c0b073de28d43770bf3b68969
URL: https://github.com/llvm/llvm-project/commit/fc03fad3dde95d9c0b073de28d43770bf3b68969 DIFF: https://github.com/llvm/llvm-project/commit/fc03fad3dde95d9c0b073de28d43770bf3b68969.diff LOG: [AArch64][GlobalISel] Lower vector G_CTTZ. Fixes issue 56398 (cherry picked from commit 9cc1dd209d20eda51710f302800899730b419381) Added: Modified: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index d3617b87a851d..380d3621e7452 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -662,8 +662,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).lower(); - // TODO: Handle vector types. getActionDefinitionsBuilder(G_CTTZ) + .lowerIf(isVector(0)) .clampScalar(0, s32, s64) .scalarSameSizeAs(1, 0) .customFor({s32, s64}); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir index 418b31d061518..0486efc665d9c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir @@ -88,3 +88,29 @@ body: | %1:_(s64) = G_CTTZ %val(s64) $x0 = COPY %1(s64) RET_ReallyLR implicit $x0 +... +--- +name: v4s32 +alignment: 4 +tracksRegLiveness: true +body: | + bb.0: + liveins: $q0 + + ; CHECK-LABEL: name: v4s32 + ; CHECK: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %val:_(<4 x s32>) = COPY $q0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR %val, [[BUILD_VECTOR]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD %val, [[BUILD_VECTOR]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[XOR]], [[ADD]] + ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<4 x s32>) = G_CTPOP [[AND]](<4 x s32>) + ; CHECK-NEXT: $q0 = COPY [[CTPOP]](<4 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 + %val:_(<4 x s32>) = COPY $q0 + %1:_(<4 x s32>) = G_CTTZ %val(<4 x s32>) + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 +... _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
