Author: Nikita Popov Date: 2023-10-17T08:12:03+02:00 New Revision: 491a91e8eea27fab4d8123cbfbb01bf1cf251b9c
URL: https://github.com/llvm/llvm-project/commit/491a91e8eea27fab4d8123cbfbb01bf1cf251b9c DIFF: https://github.com/llvm/llvm-project/commit/491a91e8eea27fab4d8123cbfbb01bf1cf251b9c.diff LOG: [PowerPC] Use zext instead of anyext in custom and combine (#68784) This custom combine currently converts `and(anyext(x),c)` into `anyext(and(x,c))`. This is not correct, because the original expression guaranteed that the high bits are zero, while the new one sets them to undef. Emit `zext(and(x,c))` instead. Fixes https://github.com/llvm/llvm-project/issues/68783. (cherry picked from commit 127ed9ae266ead58aa525f74f4c86841f6674793) Added: Modified: llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/test/CodeGen/PowerPC/and-extend-combine.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 3ed0a261eb769a1..d4d2da55160e552 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -15527,7 +15527,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, break; SDValue ConstOp = DAG.getConstant(Imm, dl, MVT::i32); SDValue NarrowAnd = DAG.getNode(ISD::AND, dl, MVT::i32, NarrowOp, ConstOp); - return DAG.getAnyExtOrTrunc(NarrowAnd, dl, N->getValueType(0)); + return DAG.getZExtOrTrunc(NarrowAnd, dl, N->getValueType(0)); } case ISD::SHL: return combineSHL(N, DCI); diff --git a/llvm/test/CodeGen/PowerPC/and-extend-combine.ll b/llvm/test/CodeGen/PowerPC/and-extend-combine.ll index 50604d8ef32afa9..1ffff5cb5fc89fc 100644 --- a/llvm/test/CodeGen/PowerPC/and-extend-combine.ll +++ b/llvm/test/CodeGen/PowerPC/and-extend-combine.ll @@ -23,11 +23,12 @@ bb: ret ptr %i8 } -; FIXME: This is a miscompile. define void @pr68783(i32 %x, ptr %p) { ; CHECK-LABEL: pr68783: ; CHECK: # %bb.0: +; CHECK-NEXT: li r5, 0 ; CHECK-NEXT: rlwinm r3, r3, 31, 24, 31 +; CHECK-NEXT: sth r5, 4(r4) ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr %lshr = lshr i32 %x, 1 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
