Author: Philip Reames Date: 2023-11-16T14:28:16-08:00 New Revision: 233971b475a48d9ad8c61632660a1b45186897cc
URL: https://github.com/llvm/llvm-project/commit/233971b475a48d9ad8c61632660a1b45186897cc DIFF: https://github.com/llvm/llvm-project/commit/233971b475a48d9ad8c61632660a1b45186897cc.diff LOG: [RISCV] Fix typo in a test and regen another to reduce test diff Added: Modified: llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll b/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll index 9193f7aef4b8757..3fc22818a2406a5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll @@ -12,16 +12,14 @@ define void @v4xi8_concat_vector_insert_idx0(ptr %a, ptr %b, i8 %x) { ; CHECK-NEXT: vle8.v v9, (a1) ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 -; CHECK-NEXT: vmv.s.x v9, a2 -; CHECK-NEXT: vsetivli zero, 2, e8, mf4, tu, ma -; CHECK-NEXT: vslideup.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, ma +; CHECK-NEXT: vmv.s.x v8, a2 ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %v1 = load <2 x i8>, ptr %a %v2 = load <2 x i8>, ptr %b %concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> - %ins = insertelement <4 x i8> %concat, i8 %x, i32 1 + %ins = insertelement <4 x i8> %concat, i8 %x, i32 0 store <4 x i8> %ins, ptr %a ret void } @@ -98,11 +96,9 @@ define void @v4xi64_concat_vector_insert_idx0(ptr %a, ptr %b, i64 %x) { ; RV32-NEXT: vle64.v v10, (a1) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV32-NEXT: vslideup.vi v8, v10, 2 -; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma -; RV32-NEXT: vslide1down.vx v10, v8, a2 -; RV32-NEXT: vslide1down.vx v10, v10, a3 -; RV32-NEXT: vsetivli zero, 2, e64, m1, tu, ma -; RV32-NEXT: vslideup.vi v8, v10, 1 +; RV32-NEXT: vsetivli zero, 2, e32, m1, tu, ma +; RV32-NEXT: vslide1down.vx v8, v8, a2 +; RV32-NEXT: vslide1down.vx v8, v8, a3 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: ret @@ -114,16 +110,14 @@ define void @v4xi64_concat_vector_insert_idx0(ptr %a, ptr %b, i64 %x) { ; RV64-NEXT: vle64.v v10, (a1) ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV64-NEXT: vslideup.vi v8, v10, 2 -; RV64-NEXT: vmv.s.x v10, a2 -; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma -; RV64-NEXT: vslideup.vi v8, v10, 1 -; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, ma +; RV64-NEXT: vmv.s.x v8, a2 ; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %v1 = load <2 x i64>, ptr %a %v2 = load <2 x i64>, ptr %b %concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> - %ins = insertelement <4 x i64> %concat, i64 %x, i32 1 + %ins = insertelement <4 x i64> %concat, i64 %x, i32 0 store <4 x i64> %ins, ptr %a ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll index d1ea56a1ff93819..2d8bae7092242d3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -1080,6 +1080,13 @@ define <32 x double> @buildvec_v32f64(double %e0, double %e1, double %e2, double ; FIXME: These constants have enough sign bits that we could use vmv.v.x/i and ; vsext, but we don't support this for FP yet. define <2 x float> @signbits() { +; CHECK-LABEL: signbits: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui a0, %hi(.LCPI24_0) +; CHECK-NEXT: addi a0, a0, %lo(.LCPI24_0) +; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret entry: ret <2 x float> <float 0x36A0000000000000, float 0.000000e+00> } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
