Author: Craig Topper Date: 2023-11-27T15:52:15-08:00 New Revision: b4cf014991bfa144306a1069ca5c1eabbb456ddd
URL: https://github.com/llvm/llvm-project/commit/b4cf014991bfa144306a1069ca5c1eabbb456ddd DIFF: https://github.com/llvm/llvm-project/commit/b4cf014991bfa144306a1069ca5c1eabbb456ddd.diff LOG: [RISCV][GISel] Select trap and debugtrap. (#73171) Added: llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir Modified: llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index f6527018d7ab828..d37026f00117995 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -71,6 +71,8 @@ class RISCVInstructionSelector : public InstructionSelector { MachineRegisterInfo &MRI) const; bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const; + bool selectIntrinsicWithSideEffects(MachineInstr &MI, MachineIRBuilder &MIB, + MachineRegisterInfo &MRI) const; ComplexRendererFns selectShiftMask(MachineOperand &Root) const; ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const; @@ -608,6 +610,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { return selectSelect(MI, MIB, MRI); case TargetOpcode::G_FCMP: return selectFPCompare(MI, MIB, MRI); + case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: + return selectIntrinsicWithSideEffects(MI, MIB, MRI); default: return false; } @@ -1060,6 +1064,29 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, return true; } +bool RISCVInstructionSelector::selectIntrinsicWithSideEffects( + MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const { + assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS && + "Unexpected opcode"); + // Find the intrinsic ID. + unsigned IntrinID = cast<GIntrinsic>(MI).getIntrinsicID(); + + // Select the instruction. + switch (IntrinID) { + default: + return false; + case Intrinsic::trap: + MIB.buildInstr(RISCV::UNIMP, {}, {}); + break; + case Intrinsic::debugtrap: + MIB.buildInstr(RISCV::EBREAK, {}, {}); + break; + } + + MI.eraseFromParent(); + return true; +} + namespace llvm { InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir new file mode 100644 index 000000000000000..11789a030e6fac0 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir @@ -0,0 +1,34 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: test_trap +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: test_trap + ; CHECK: UNIMP + ; CHECK-NEXT: PseudoRET + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap) + PseudoRET + +... +--- +name: test_debugtrap +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: test_debugtrap + ; CHECK: EBREAK + ; CHECK-NEXT: PseudoRET + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.debugtrap) + PseudoRET + +... _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
