[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

[David Green via llvm-branch-commits]

================
@@ -1070,6 +1070,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const 
AArch64Subtarget &ST)
                  {s16, v8s16},
                  {s32, v2s32},
                  {s32, v4s32}})
+      .moreElementsIf(
----------------
davemgreen wrote:

I think this can happen for more than just odd numbers, if we have support in 
the legalizer. I think I would make it moreElementsToNextPow2 unless there is a 
big reason not to.

https://github.com/llvm/llvm-project/pull/81831
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