[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

[Fangrui Song via llvm-branch-commits]

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@@ -126,9 +126,9 @@ enum NodeType : unsigned {
   // Floating point fmax and fmin matching the RISC-V instruction semantics.
   FMAX, FMIN,
 
-  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
+  // READ_COUNTER_WIDE - A read of the 64-bit counter CSR on a 32-bit target
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MaskRay wrote:

For new code, we don't replicate the variable/function name.

https://github.com/llvm/llvm-project/pull/82322
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