https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/82664
Backport b0edc1c45284586fdb12edd666f95d99f5f62b43
Requested by: @OMaghiarIMG
>From 5994086729d9c28d8ea4059871c39c022097dc6b Mon Sep 17 00:00:00 2001
From: Luke Lau <l...@igalia.com>
Date: Fri, 23 Feb 2024 01:49:19 +0800
Subject: [PATCH] [Loads] Fix crash in isSafeToLoadUnconditionally with
scalable accessed type (#82650)
This fixes #82606 by updating isSafeToLoadUnconditionally to handle
fixed sized loads from a scalable accessed type.
(cherry picked from commit b0edc1c45284586fdb12edd666f95d99f5f62b43)
---
llvm/lib/Analysis/Loads.cpp | 6 +++---
.../VectorCombine/RISCV/load-widening.ll | 19 +++++++++++++++++++
2 files changed, 22 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/Transforms/VectorCombine/RISCV/load-widening.ll
diff --git a/llvm/lib/Analysis/Loads.cpp b/llvm/lib/Analysis/Loads.cpp
index 6bf0d2f56eb4eb..5916d2ab48ecec 100644
--- a/llvm/lib/Analysis/Loads.cpp
+++ b/llvm/lib/Analysis/Loads.cpp
@@ -364,7 +364,7 @@ bool llvm::isSafeToLoadUnconditionally(Value *V, Align
Alignment, APInt &Size,
if (Size.getBitWidth() > 64)
return false;
- const uint64_t LoadSize = Size.getZExtValue();
+ const TypeSize LoadSize = TypeSize::getFixed(Size.getZExtValue());
// Otherwise, be a little bit aggressive by scanning the local block where we
// want to check to see if the pointer is already being loaded or stored
@@ -414,11 +414,11 @@ bool llvm::isSafeToLoadUnconditionally(Value *V, Align
Alignment, APInt &Size,
// Handle trivial cases.
if (AccessedPtr == V &&
- LoadSize <= DL.getTypeStoreSize(AccessedTy))
+ TypeSize::isKnownLE(LoadSize, DL.getTypeStoreSize(AccessedTy)))
return true;
if (AreEquivalentAddressValues(AccessedPtr->stripPointerCasts(), V) &&
- LoadSize <= DL.getTypeStoreSize(AccessedTy))
+ TypeSize::isKnownLE(LoadSize, DL.getTypeStoreSize(AccessedTy)))
return true;
}
return false;
diff --git a/llvm/test/Transforms/VectorCombine/RISCV/load-widening.ll
b/llvm/test/Transforms/VectorCombine/RISCV/load-widening.ll
new file mode 100644
index 00000000000000..0a43ad2f9a3684
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/RISCV/load-widening.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
+; RUN: opt < %s -passes=vector-combine -S -mtriple=riscv32 -mattr=+v |
FileCheck %s
+; RUN: opt < %s -passes=vector-combine -S -mtriple=riscv64 -mattr=+v |
FileCheck %s
+
+define void @fixed_load_scalable_src(ptr %p) {
+; CHECK-LABEL: define void @fixed_load_scalable_src(
+; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: store <vscale x 4 x i16> zeroinitializer, ptr [[P]], align 8
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[P]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16>
zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison,
i32 poison, i32 poison>
+; CHECK-NEXT: ret void
+;
+entry:
+ store <vscale x 4 x i16> zeroinitializer, ptr %p
+ %0 = load <4 x i16>, ptr %p
+ %1 = shufflevector <4 x i16> %0, <4 x i16> zeroinitializer, <8 x i32> <i32
0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+ ret void
+}
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