Author: Rose Date: 2024-04-24T15:11:22-07:00 New Revision: 76cbd417af50b444f5fbaa628b5a76064e6f10db
URL: https://github.com/llvm/llvm-project/commit/76cbd417af50b444f5fbaa628b5a76064e6f10db DIFF: https://github.com/llvm/llvm-project/commit/76cbd417af50b444f5fbaa628b5a76064e6f10db.diff LOG: [X86] Pre-commit tests (NFC) Added: Modified: llvm/test/CodeGen/X86/sar_fold.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/X86/sar_fold.ll b/llvm/test/CodeGen/X86/sar_fold.ll index 21655e19440afe..22ae8e8abd3eca 100644 --- a/llvm/test/CodeGen/X86/sar_fold.ll +++ b/llvm/test/CodeGen/X86/sar_fold.ll @@ -44,3 +44,44 @@ define i32 @shl24sar25(i32 %a) #0 { %2 = ashr exact i32 %1, 25 ret i32 %2 } + +define void @shl144sar48(ptr %p) #0 { +; CHECK-LABEL: shl144sar48: +; CHECK: # %bb.0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movswl (%eax), %ecx +; CHECK-NEXT: movl %ecx, %edx +; CHECK-NEXT: sarl $31, %edx +; CHECK-NEXT: shldl $2, %ecx, %edx +; CHECK-NEXT: shll $2, %ecx +; CHECK-NEXT: movl %ecx, 12(%eax) +; CHECK-NEXT: movl %edx, 16(%eax) +; CHECK-NEXT: movl $0, 8(%eax) +; CHECK-NEXT: movl $0, 4(%eax) +; CHECK-NEXT: movl $0, (%eax) +; CHECK-NEXT: retl + %a = load i160, ptr %p + %1 = shl i160 %a, 144 + %2 = ashr exact i160 %1, 46 + store i160 %2, ptr %p + ret void +} + +define void @shl144sar2(ptr %p) #0 { +; CHECK-LABEL: shl144sar2: +; CHECK: # %bb.0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movswl (%eax), %ecx +; CHECK-NEXT: sarl $31, %ecx +; CHECK-NEXT: movl %ecx, 16(%eax) +; CHECK-NEXT: movl %ecx, 8(%eax) +; CHECK-NEXT: movl %ecx, 12(%eax) +; CHECK-NEXT: movl %ecx, 4(%eax) +; CHECK-NEXT: movl %ecx, (%eax) +; CHECK-NEXT: retl + %a = load i160, ptr %p + %1 = shl i160 %a, 144 + %2 = ashr exact i160 %1, 2 + store i160 %2, ptr %p + ret void +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
