topperc wrote: > For saturating instructions, they may write vxsat. This is like floating-point instructions that may write fflags, but we don't model floating-point instructions as hasSideEffects=1.
That's because floating point instructions use mayRaiseFPExceptions=1. And STRICT_* nodes set don't set the NoFPExcept bit in MIFlags. Though we don't have a story for how to make reading FFLAGS work with riscv.* intrinsics. That's an issue on all targets as there is no "constrained" or "strict" support for target specific intrinsics. https://github.com/llvm/llvm-project/pull/90049 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
