Author: Yingwei Zheng Date: 2024-05-01T11:39:11-07:00 New Revision: 20b9ed64ea074f03057e1d775a1d9d0f067ab0b0
URL: https://github.com/llvm/llvm-project/commit/20b9ed64ea074f03057e1d775a1d9d0f067ab0b0 DIFF: https://github.com/llvm/llvm-project/commit/20b9ed64ea074f03057e1d775a1d9d0f067ab0b0.diff LOG: [RISCV][ISel] Fix types in `tryFoldSelectIntoOp` (#90659) ``` SelectionDAG has 17 nodes: t0: ch,glue = EntryToken t6: i64,ch = CopyFromReg t0, Register:i64 %2 t8: i1 = truncate t6 t4: i64,ch = CopyFromReg t0, Register:i64 %1 t7: i1 = truncate t4 t2: i64,ch = CopyFromReg t0, Register:i64 %0 t10: i64,i1 = saddo t2, Constant:i64<1> t11: i1 = or t8, t10:1 t12: i1 = select t7, t8, t11 t13: i64 = any_extend t12 t15: ch,glue = CopyToReg t0, Register:i64 $x10, t13 t16: ch = RISCVISD::RET_GLUE t15, Register:i64 $x10, t15:1 ``` `OtherOpVT` should be i1, but `OtherOp->getValueType(0)` returns `i64`, which ignores `ResNo` in `SDValue`. Fix https://github.com/llvm/llvm-project/issues/90652. (cherry picked from commit 2647bd73696ae987addd0e74774a44108accb1e6) Added: llvm/test/CodeGen/RISCV/pr90652.ll Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a0cec426002b6f..d46093b9e260a2 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14559,7 +14559,7 @@ static SDValue tryFoldSelectIntoOp(SDNode *N, SelectionDAG &DAG, EVT VT = N->getValueType(0); SDLoc DL(N); SDValue OtherOp = TrueVal.getOperand(1 - OpToFold); - EVT OtherOpVT = OtherOp->getValueType(0); + EVT OtherOpVT = OtherOp.getValueType(); SDValue IdentityOperand = DAG.getNeutralElement(Opc, DL, OtherOpVT, N->getFlags()); if (!Commutative) diff --git a/llvm/test/CodeGen/RISCV/pr90652.ll b/llvm/test/CodeGen/RISCV/pr90652.ll new file mode 100644 index 00000000000000..2162395b92ac3c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/pr90652.ll @@ -0,0 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=riscv64 | FileCheck %s + +define i1 @test(i64 %x, i1 %cond1, i1 %cond2) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi a3, a0, 1 +; CHECK-NEXT: slt a0, a3, a0 +; CHECK-NEXT: not a1, a1 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: or a0, a2, a0 +; CHECK-NEXT: ret +entry: + %sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %x, i64 1) + %ov = extractvalue { i64, i1 } %sadd, 1 + %or = or i1 %cond2, %ov + %sel = select i1 %cond1, i1 %cond2, i1 %or + ret i1 %sel +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
