================
@@ -49,7 +49,7 @@ void test_s_wait_event_export_ready() {
}
// CHECK-LABEL: @test_global_add_f32
-// CHECK: {{.*}}call{{.*}} float
@llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %{{.*}}, float
%{{.*}})
+// CHECK: = atomicrmw fadd ptr addrspace(1) %addr, float %x syncscope("agent")
seq_cst, align 4, !amdgpu.no.fine.grained.memory !{{[0-9]+}},
!amdgpu.ignore.denormal.mode !{{[0-9]+$}}
----------------
yxsamliu wrote:
why the memory order is seq_cst ? Does this generate the same ISA as before?
Can we add some test to emit assembly directly by clang to make sure the ISA
does not change?
https://github.com/llvm/llvm-project/pull/96872
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