================
@@ -36,38 +32,43 @@ using namespace llvm;
#define AARCH64_SLS_HARDENING_NAME "AArch64 sls hardening pass"
+static const char SLSBLRNamePrefix[] = "__llvm_slsblr_thunk_";
+
namespace {
-class AArch64SLSHardening : public MachineFunctionPass {
-public:
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const AArch64Subtarget *ST;
+// Set of inserted thunks: bitmask with bits corresponding to
+// indexes in SLSBLRThunks array.
+typedef uint32_t ThunksSet;
----------------
kbeyls wrote:
I guess once support for BLRA* instruction will be added, the bitset may
contain up to 29\*29-ish registers and this typedef will change to something
different than a `uint32_t`?
I agree this can be done in the follow-on patch that will support BLRA*
instructions.
https://github.com/llvm/llvm-project/pull/97472
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