https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/104747
Backport 65ac12d3c9877ecf5b97552364e7eead887d94eb
56140a8258a3498cfcd9f0f05c182457d43cbfd2
Requested by: @nikic
>From 92cec47736ec4ba1ef33649660a4fc21bdd8e57e Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bat...@outlook.com>
Date: Thu, 15 Aug 2024 07:21:10 -0700
Subject: [PATCH 1/2] [SLP][NFC]Add a test with incorrect minbitwidth analysis
for reduced operands
(cherry picked from commit 65ac12d3c9877ecf5b97552364e7eead887d94eb)
---
.../X86/operand-is-reduced-val.ll | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644
llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
b/llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
new file mode 100644
index 00000000000000..5fb93e27539d8e
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux < %s
-slp-threshold=-10 | FileCheck %s
+
+define i64 @src(i32 %a) {
+; CHECK-LABEL: define i64 @src(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP17:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32>
poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[TMP2]], <i32 1, i32 1, i32 1,
i32 1>
+; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i32> [[TMP3]] to <4 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i32> [[TMP3]], <i32 1, i32 1, i32 1,
i32 1>
+; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i32> [[TMP5]] to <4 x i64>
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x
i64> [[TMP6]])
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x
i64> [[TMP4]])
+; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[TMP18]], [[TMP16]]
+; CHECK-NEXT: [[OP_RDX1:%.*]] = add i64 [[TMP19]], 4294967297
+; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[OP_RDX1]], [[TMP17]]
+; CHECK-NEXT: ret i64 [[TMP21]]
+;
+entry:
+ %0 = sext i32 %a to i64
+ %1 = add nsw i64 %0, 4294967297
+ %2 = sext i32 %a to i64
+ %3 = add nsw i64 %2, 4294967297
+ %4 = add i64 %3, %1
+ %5 = and i64 %3, 1
+ %6 = add i64 %4, %5
+ %7 = sext i32 %a to i64
+ %8 = add nsw i64 %7, 4294967297
+ %9 = add i64 %8, %6
+ %10 = and i64 %8, 1
+ %11 = add i64 %9, %10
+ %12 = sext i32 %a to i64
+ %13 = add nsw i64 %12, 4294967297
+ %14 = add i64 %13, %11
+ %15 = and i64 %13, 1
+ %16 = add i64 %14, %15
+ %17 = sext i32 %a to i64
+ %18 = add nsw i64 %17, 4294967297
+ %19 = add i64 %18, %16
+ %20 = and i64 %18, 1
+ %21 = add i64 %19, %20
+ ret i64 %21
+}
>From 60b6cb6403168fbb62f1dd79083ac768d747edb9 Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bat...@outlook.com>
Date: Thu, 15 Aug 2024 07:57:37 -0700
Subject: [PATCH 2/2] [SLP]Fix PR104422: Wrong value truncation
The minbitwidth restrictions can be skipped only for immediate reduced
values, for other nodes still need to check if external users allow
bitwidth reduction.
Fixes https://github.com/llvm/llvm-project/issues/104422
(cherry picked from commit 56140a8258a3498cfcd9f0f05c182457d43cbfd2)
---
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 3 ++-
.../SLPVectorizer/X86/operand-is-reduced-val.ll | 17 ++++++++++-------
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index cca9eeebaa53f0..0cddc510d36dac 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -15211,7 +15211,8 @@ bool BoUpSLP::collectValuesToDemote(
if (any_of(E.Scalars, [&](Value *V) {
return !all_of(V->users(), [=](User *U) {
return getTreeEntry(U) ||
- (UserIgnoreList && UserIgnoreList->contains(U)) ||
+ (E.Idx == 0 && UserIgnoreList &&
+ UserIgnoreList->contains(U)) ||
(!isa<CmpInst>(U) && U->getType()->isSized() &&
!U->getType()->isScalableTy() &&
DL->getTypeSizeInBits(U->getType()) <= BitWidth);
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
b/llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
index 5fb93e27539d8e..5fcac3fbf3bafe 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll
@@ -8,15 +8,18 @@ define i64 @src(i32 %a) {
; CHECK-NEXT: [[TMP17:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32>
poison, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[TMP2]], <i32 1, i32 1, i32 1,
i32 1>
-; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i32> [[TMP3]] to <4 x i64>
-; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i32> [[TMP3]], <i32 1, i32 1, i32 1,
i32 1>
-; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i32> [[TMP5]] to <4 x i64>
+; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>
+; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i64> [[TMP3]], <i64 4294967297,
i64 4294967297, i64 4294967297, i64 4294967297>
+; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i64> [[TMP4]], <i64 1, i64 1, i64 1,
i64 1>
; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x
i64> [[TMP6]])
; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x
i64> [[TMP4]])
-; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[TMP18]], [[TMP16]]
-; CHECK-NEXT: [[OP_RDX1:%.*]] = add i64 [[TMP19]], 4294967297
-; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[OP_RDX1]], [[TMP17]]
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[TMP16]],
i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> [[TMP8]], i64
[[TMP18]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> <i64 poison, i64
4294967297>, i64 [[TMP17]], i32 0
+; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[TMP9]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i64> [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i64> [[TMP11]], i32 1
+; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP12]], [[TMP13]]
; CHECK-NEXT: ret i64 [[TMP21]]
;
entry:
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