================
@@ -27056,21 +27056,35 @@
AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
: AtomicExpansionKind::LLSC;
}
+// Return true if the atomic operation expansion will lower to use a library
+// call, and is thus ineligible to use an LLSC expansion.
+static bool rmwOpMayLowerToLibcall(const AtomicRMWInst *RMW) {
+ if (!RMW->isFloatingPointOperation())
+ return false;
+ switch (RMW->getType()->getScalarType()->getTypeID()) {
+ case Type::FloatTyID:
+ case Type::DoubleTyID:
+ case Type::HalfTyID:
+ case Type::BFloatTyID:
+ return false;
----------------
efriedma-quic wrote:
(I'm confident Subtarget->hasFPARMv8() is the right check; it's the same check
used to enable the registers.)
https://github.com/llvm/llvm-project/pull/103702
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