================ @@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion( } return Considerable; } + +RISCVTTIImpl::TTI::MemCmpExpansionOptions +RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { + TTI::MemCmpExpansionOptions Options; + // FIXME: Vector haven't been tested. + Options.AllowOverlappingLoads = + (ST->enableUnalignedScalarMem() || ST->enableUnalignedVectorMem()); + Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); + Options.NumLoadsPerBlock = Options.MaxNumLoads; + if (ST->is64Bit()) + Options.LoadSizes.push_back(8); + llvm::append_range(Options.LoadSizes, ArrayRef({4, 2, 1})); + Options.AllowedTailExpansions = {3, 5, 6}; ---------------- wangpc-pp wrote:
I removed it first. If RISC-V can benefit from it, we can add it back as a follow-up. https://github.com/llvm/llvm-project/pull/107548 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits