https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From d9957fa8395cb0754fdf935fec55123284e15b30 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Mon, 4 Nov 2024 06:58:14 +0000
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/include/llvm/CodeGen/TargetPassConfig.h | 8 --------
llvm/include/llvm/Target/TargetOptions.h | 8 +++++++-
llvm/lib/CodeGen/MachineSink.cpp | 4 +++-
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +-
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h
b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..b395774b14c441 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge = true;
- /// Enable sinking of instructions in MachineSink where a computation can be
- /// folded into the addressing mode of a memory load/store instruction or
- /// replace a copy.
- bool EnableSinkAndFold = false;
-
/// Require processing of functions such that callees are generated before
/// callers.
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
- bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
- void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
-
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
void setRequiresCodeGenSCCOrder(bool Enable = true) {
setOpt(RequireCodeGenSCCOrder, Enable);
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 88f253805ca99c..b16ad5b69ff05a 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,7 +137,8 @@ namespace llvm {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableSinkAndFold(false), EnableFastISel(false),
+ EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
/// they were generated. Default is true.
unsigned StackSymbolOrdering : 1;
+ /// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
+ /// a computation can be folded into the addressing mode of a memory
+ /// load/store instruction or replace a copy.
+ unsigned EnableSinkAndFold : 1;
+
/// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing
/// compile time.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..6849a3f12d8cfd 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -54,6 +54,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
@@ -729,7 +730,8 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+ auto &TM = PassConfig->getTM<TargetMachine>();
+ EnableSinkAndFold = TM.Options.EnableSinkAndFold;
bool EverMadeChange = false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b65620..ee8aae4ee8bcc8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
- setEnableSinkAndFold(EnableSinkFold);
+ TM.Options.EnableSinkAndFold = EnableSinkFold;
}
AArch64TargetMachine &getAArch64TargetMachine() const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 72d74d2d79b1d5..00653ca348476e 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -337,7 +337,7 @@ class RISCVPassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
- setEnableSinkAndFold(EnableSinkFold);
+ TM.Options.EnableSinkAndFold = EnableSinkFold;
EnableLoopTermFold = true;
}
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