https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/113874
>From a95b69c07c7804d2e2a10b939a178a191643a41c Mon Sep 17 00:00:00 2001 From: Akshat Oke <akshat....@amd.com> Date: Mon, 28 Oct 2024 06:22:49 +0000 Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM --- .../llvm/CodeGen/RegUsageInfoCollector.h | 25 ++++++++ llvm/include/llvm/InitializePasses.h | 2 +- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 + .../llvm/Passes/MachinePassRegistry.def | 2 +- llvm/lib/CodeGen/CodeGen.cpp | 2 +- llvm/lib/CodeGen/RegUsageInfoCollector.cpp | 60 +++++++++++++------ llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 5 ++ 8 files changed, 76 insertions(+), 22 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoCollector.h diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h new file mode 100644 index 00000000000000..6b88cc4f99089e --- /dev/null +++ b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h @@ -0,0 +1,25 @@ +//===- llvm/CodeGen/RegUsageInfoCollector.h ---------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H +#define LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H + +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { + +class RegUsageInfoCollectorPass + : public AnalysisInfoMixin<RegUsageInfoCollectorPass> { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index edc237f2819818..44b7ba830bb329 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -257,7 +257,7 @@ void initializeRegAllocPriorityAdvisorAnalysisPass(PassRegistry &); void initializeRegAllocScoringPass(PassRegistry &); void initializeRegBankSelectPass(PassRegistry &); void initializeRegToMemWrapperPassPass(PassRegistry &); -void initializeRegUsageInfoCollectorPass(PassRegistry &); +void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &); void initializeRegUsageInfoPropagationPass(PassRegistry &); void initializeRegionInfoPassPass(PassRegistry &); void initializeRegionOnlyPrinterPass(PassRegistry &); diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 8cbc9f71ab26d0..066cd70ec8b996 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -53,6 +53,7 @@ #include "llvm/CodeGen/PHIElimination.h" #include "llvm/CodeGen/PreISelIntrinsicLowering.h" #include "llvm/CodeGen/RegAllocFast.h" +#include "llvm/CodeGen/RegUsageInfoCollector.h" #include "llvm/CodeGen/RegisterUsageInfo.h" #include "llvm/CodeGen/ReplaceWithVeclib.h" #include "llvm/CodeGen/SafeStack.h" diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 7db28cb0092525..0ee4794034e98b 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -156,6 +156,7 @@ MACHINE_FUNCTION_PASS("print<machine-post-dom-tree>", MachinePostDominatorTreePrinterPass(dbgs())) MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(dbgs())) MACHINE_FUNCTION_PASS("print<virtregmap>", VirtRegMapPrinterPass(dbgs())) +MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass()) MACHINE_FUNCTION_PASS("require-all-machine-function-properties", RequireAllMachineFunctionPropertiesPass()) MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass()) @@ -250,7 +251,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass) DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass) DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass) DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass) -DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass) DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass) DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass) DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass) diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 39fba1d0b527ef..e7e8a121369b75 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -113,7 +113,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeRABasicPass(Registry); initializeRAGreedyPass(Registry); initializeRegAllocFastPass(Registry); - initializeRegUsageInfoCollectorPass(Registry); + initializeRegUsageInfoCollectorLegacyPass(Registry); initializeRegUsageInfoPropagationPass(Registry); initializeRegisterCoalescerPass(Registry); initializeRemoveLoadsIntoFakeUsesPass(Registry); diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index fc7664e2ba2357..b033ccf1780139 100644 --- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -16,9 +16,11 @@ /// //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/RegUsageInfoCollector.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegisterUsageInfo.h" @@ -36,11 +38,23 @@ STATISTIC(NumCSROpt, namespace { -class RegUsageInfoCollector : public MachineFunctionPass { +class RegUsageInfoCollector { + PhysicalRegisterUsageInfo &PRUI; + +public: + RegUsageInfoCollector(PhysicalRegisterUsageInfo &PRUI) : PRUI(PRUI) {} + bool run(MachineFunction &MF); + + // Call getCalleeSaves and then also set the bits for subregs and + // fully saved superregs. + static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF); +}; + +class RegUsageInfoCollectorLegacy : public MachineFunctionPass { public: - RegUsageInfoCollector() : MachineFunctionPass(ID) { - PassRegistry &Registry = *PassRegistry::getPassRegistry(); - initializeRegUsageInfoCollectorPass(Registry); + static char ID; + RegUsageInfoCollectorLegacy() : MachineFunctionPass(ID) { + initializeRegUsageInfoCollectorLegacyPass(*PassRegistry::getPassRegistry()); } StringRef getPassName() const override { @@ -54,26 +68,19 @@ class RegUsageInfoCollector : public MachineFunctionPass { } bool runOnMachineFunction(MachineFunction &MF) override; - - // Call getCalleeSaves and then also set the bits for subregs and - // fully saved superregs. - static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF); - - static char ID; }; - } // end of anonymous namespace -char RegUsageInfoCollector::ID = 0; +char RegUsageInfoCollectorLegacy::ID = 0; -INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector", +INITIALIZE_PASS_BEGIN(RegUsageInfoCollectorLegacy, "RegUsageInfoCollector", "Register Usage Information Collector", false, false) INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfoWrapperLegacy) -INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector", +INITIALIZE_PASS_END(RegUsageInfoCollectorLegacy, "RegUsageInfoCollector", "Register Usage Information Collector", false, false) FunctionPass *llvm::createRegUsageInfoCollector() { - return new RegUsageInfoCollector(); + return new RegUsageInfoCollectorLegacy(); } // TODO: Move to hook somwehere? @@ -97,12 +104,29 @@ static bool isCallableFunction(const MachineFunction &MF) { } } -bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { +PreservedAnalyses +RegUsageInfoCollectorPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + Module &MFA = *MF.getFunction().getParent(); + auto *PRUI = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF) + .getCachedResult<PhysicalRegisterUsageInfoAnalysis>(MFA); + assert(PRUI && "PhysicalRegisterUsageInfoAnalysis not available"); + RegUsageInfoCollector(*PRUI).run(MF); + return PreservedAnalyses::all(); +} + +bool RegUsageInfoCollectorLegacy::runOnMachineFunction(MachineFunction &MF) { + PhysicalRegisterUsageInfo &PRUI = + getAnalysis<PhysicalRegisterUsageInfoWrapperLegacy>().getPRUI(); + return RegUsageInfoCollector(PRUI).run(MF); +} + +bool RegUsageInfoCollector::run(MachineFunction &MF) { MachineRegisterInfo *MRI = &MF.getRegInfo(); const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); const LLVMTargetMachine &TM = MF.getTarget(); - LLVM_DEBUG(dbgs() << " -------------------- " << getPassName() + LLVM_DEBUG(dbgs() << " -------------------- Reg Usage Info Collector" << " -------------------- \nFunction Name : " << MF.getName() << '\n'); @@ -129,8 +153,6 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { const Function &F = MF.getFunction(); - PhysicalRegisterUsageInfo &PRUI = - getAnalysis<PhysicalRegisterUsageInfoWrapperLegacy>().getPRUI(); PRUI.setTargetMachine(TM); LLVM_DEBUG(dbgs() << "Clobbered Registers: "); diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index b9fbbf72026aa2..902eff2a0611f8 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -118,6 +118,7 @@ #include "llvm/CodeGen/PHIElimination.h" #include "llvm/CodeGen/PreISelIntrinsicLowering.h" #include "llvm/CodeGen/RegAllocFast.h" +#include "llvm/CodeGen/RegUsageInfoCollector.h" #include "llvm/CodeGen/RegisterUsageInfo.h" #include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/SelectOptimize.h" diff --git a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll index 492ad9561875c8..e41e1057a2a1d1 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll @@ -1,5 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \ +; RUN: | llc -x=mir -mtriple=amdgcn-amd-amdhsa -passes="module(require<reg-usage-info>,function(machine-function(reg-usage-collector)),print<regusage>)" -o /dev/null 2>&1 \ +; RUN: | FileCheck %s + ; Make sure the expected regmask is generated for sub/superregisters. ; CHECK-DAG: csr Clobbered Registers: $vgpr0 $vgpr0_hi16 $vgpr0_lo16 $vgpr0_vgpr1 $vgpr0_vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 {{$}} >From 8abd62fa7af504212b3b9a244e974d24cfcc1b8a Mon Sep 17 00:00:00 2001 From: Akshat Oke <akshat....@amd.com> Date: Mon, 28 Oct 2024 07:32:33 +0000 Subject: [PATCH 2/5] update tests and pass name in debug --- llvm/include/llvm/CodeGen/RegisterUsageInfo.h | 3 --- llvm/lib/CodeGen/RegUsageInfoCollector.cpp | 7 ++++--- llvm/test/CodeGen/X86/ipra-inline-asm.ll | 4 ++++ llvm/test/CodeGen/X86/ipra-reg-usage.ll | 4 ++++ 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h index 2f93bfdcec535b..4811bbaf823086 100644 --- a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h +++ b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h @@ -51,9 +51,6 @@ class PhysicalRegisterUsageInfo { void print(raw_ostream &OS, const Module *M = nullptr) const; - bool invalidate(Module &M, const PreservedAnalyses &PA, - ModuleAnalysisManager::Invalidator &Inv); - private: /// A Dense map from Function * to RegMask. /// In RegMask 0 means register used (clobbered) by function. diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index b033ccf1780139..4f5c7f6efe3280 100644 --- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -126,9 +126,10 @@ bool RegUsageInfoCollector::run(MachineFunction &MF) { const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); const LLVMTargetMachine &TM = MF.getTarget(); - LLVM_DEBUG(dbgs() << " -------------------- Reg Usage Info Collector" - << " -------------------- \nFunction Name : " - << MF.getName() << '\n'); + LLVM_DEBUG( + dbgs() + << " -------------------- Register Usage Information Collector Pass" + << " -------------------- \nFunction Name : " << MF.getName() << '\n'); // Analyzing the register usage may be expensive on some targets. if (!isCallableFunction(MF)) { diff --git a/llvm/test/CodeGen/X86/ipra-inline-asm.ll b/llvm/test/CodeGen/X86/ipra-inline-asm.ll index 112c142c9f7f69..9c3fa38e330056 100644 --- a/llvm/test/CodeGen/X86/ipra-inline-asm.ll +++ b/llvm/test/CodeGen/X86/ipra-inline-asm.ll @@ -1,5 +1,9 @@ ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s +; RUN: llc --stop-after=irtranslator -o - %s \ +; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage-info>,function(machine-function(reg-usage-collector)),print<regusage>)" -o /dev/null 2>&1 \ +; RUN: | FileCheck %s + target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.12.0" diff --git a/llvm/test/CodeGen/X86/ipra-reg-usage.ll b/llvm/test/CodeGen/X86/ipra-reg-usage.ll index d1b8be15a2d034..313c58d25713c7 100644 --- a/llvm/test/CodeGen/X86/ipra-reg-usage.ll +++ b/llvm/test/CodeGen/X86/ipra-reg-usage.ll @@ -1,5 +1,9 @@ ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s +; RUN: llc -stop-after=irtranslator -o - %s \ +; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage-info>,function(machine-function(reg-usage-collector)),print<regusage>)" -o /dev/null 2>&1 \ +; RUN: | FileCheck %s + target triple = "x86_64-unknown-unknown" declare void @bar1() define preserve_allcc void @foo()#0 { >From 2ef89b1ca95b66bf75bf72174239285a63d261fa Mon Sep 17 00:00:00 2001 From: Akshat Oke <akshat....@amd.com> Date: Mon, 28 Oct 2024 09:17:16 +0000 Subject: [PATCH 3/5] fix incorrect changes --- llvm/include/llvm/CodeGen/RegisterUsageInfo.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h index 4811bbaf823086..2f93bfdcec535b 100644 --- a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h +++ b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h @@ -51,6 +51,9 @@ class PhysicalRegisterUsageInfo { void print(raw_ostream &OS, const Module *M = nullptr) const; + bool invalidate(Module &M, const PreservedAnalyses &PA, + ModuleAnalysisManager::Invalidator &Inv); + private: /// A Dense map from Function * to RegMask. /// In RegMask 0 means register used (clobbered) by function. >From 5a318a84c3cced6481f0aa7149a9002a9e6e58bd Mon Sep 17 00:00:00 2001 From: Akshat Oke <akshat....@amd.com> Date: Wed, 30 Oct 2024 06:56:47 +0000 Subject: [PATCH 4/5] propagate PhysicalRegisterUsageAnalysis renaming --- llvm/lib/CodeGen/RegUsageInfoCollector.cpp | 4 ++-- llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 2 +- llvm/test/CodeGen/X86/ipra-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/ipra-reg-usage.ll | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index 4f5c7f6efe3280..b7fca5419ae9c0 100644 --- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -109,8 +109,8 @@ RegUsageInfoCollectorPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { Module &MFA = *MF.getFunction().getParent(); auto *PRUI = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF) - .getCachedResult<PhysicalRegisterUsageInfoAnalysis>(MFA); - assert(PRUI && "PhysicalRegisterUsageInfoAnalysis not available"); + .getCachedResult<PhysicalRegisterUsageAnalysis>(MFA); + assert(PRUI && "PhysicalRegisterUsageAnalysis not available"); RegUsageInfoCollector(*PRUI).run(MF); return PreservedAnalyses::all(); } diff --git a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll index e41e1057a2a1d1..ef413a75ad2a95 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \ -; RUN: | llc -x=mir -mtriple=amdgcn-amd-amdhsa -passes="module(require<reg-usage-info>,function(machine-function(reg-usage-collector)),print<regusage>)" -o /dev/null 2>&1 \ +; RUN: | llc -x=mir -mtriple=amdgcn-amd-amdhsa -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \ ; RUN: | FileCheck %s ; Make sure the expected regmask is generated for sub/superregisters. diff --git a/llvm/test/CodeGen/X86/ipra-inline-asm.ll b/llvm/test/CodeGen/X86/ipra-inline-asm.ll index 9c3fa38e330056..c1649c7c55ebc2 100644 --- a/llvm/test/CodeGen/X86/ipra-inline-asm.ll +++ b/llvm/test/CodeGen/X86/ipra-inline-asm.ll @@ -1,7 +1,7 @@ ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s ; RUN: llc --stop-after=irtranslator -o - %s \ -; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage-info>,function(machine-function(reg-usage-collector)),print<regusage>)" -o /dev/null 2>&1 \ +; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \ ; RUN: | FileCheck %s target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/CodeGen/X86/ipra-reg-usage.ll b/llvm/test/CodeGen/X86/ipra-reg-usage.ll index 313c58d25713c7..233a723342f9a7 100644 --- a/llvm/test/CodeGen/X86/ipra-reg-usage.ll +++ b/llvm/test/CodeGen/X86/ipra-reg-usage.ll @@ -1,7 +1,7 @@ ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s ; RUN: llc -stop-after=irtranslator -o - %s \ -; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage-info>,function(machine-function(reg-usage-collector)),print<regusage>)" -o /dev/null 2>&1 \ +; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \ ; RUN: | FileCheck %s target triple = "x86_64-unknown-unknown" >From 97eb13a7a03473b17b22bc567c57acd22f1347bb Mon Sep 17 00:00:00 2001 From: Akshat Oke <akshat....@amd.com> Date: Mon, 4 Nov 2024 10:59:37 +0000 Subject: [PATCH 5/5] change irtranslator to prologepilog --- llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 2 +- llvm/test/CodeGen/X86/ipra-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/ipra-reg-usage.ll | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll index ef413a75ad2a95..a1313377f1eaf5 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=prologepilog -o - %s \ ; RUN: | llc -x=mir -mtriple=amdgcn-amd-amdhsa -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \ ; RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/X86/ipra-inline-asm.ll b/llvm/test/CodeGen/X86/ipra-inline-asm.ll index c1649c7c55ebc2..09b8bdd7900917 100644 --- a/llvm/test/CodeGen/X86/ipra-inline-asm.ll +++ b/llvm/test/CodeGen/X86/ipra-inline-asm.ll @@ -1,6 +1,6 @@ ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s -; RUN: llc --stop-after=irtranslator -o - %s \ +; RUN: llc --stop-after=prologepilog -o - %s \ ; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \ ; RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/X86/ipra-reg-usage.ll b/llvm/test/CodeGen/X86/ipra-reg-usage.ll index 233a723342f9a7..23363d81e038bc 100644 --- a/llvm/test/CodeGen/X86/ipra-reg-usage.ll +++ b/llvm/test/CodeGen/X86/ipra-reg-usage.ll @@ -1,6 +1,6 @@ ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s -; RUN: llc -stop-after=irtranslator -o - %s \ +; RUN: llc -stop-after=prologepilog -o - %s \ ; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \ ; RUN: | FileCheck %s _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
