================
@@ -674,6 +674,14 @@ class MachineRegisterInfo {
return dyn_cast_if_present<const TargetRegisterClass *>(Val);
}
+ /// Return the register bank of \p Reg.
+ /// This shouldn't be used directly unless \p Reg has a register bank.
+ const RegisterBank *getRegBank(Register Reg) const {
+ assert(isa<const RegisterBank *>(VRegInfo[Reg.id()].first) &&
+ "Register bank not set, wrong accessor");
----------------
arsenm wrote:
Assert redundant with the `cast<>`
https://github.com/llvm/llvm-project/pull/112864
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