https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/124512
>From 8d6f4a951cb38399ca83a7e6d14fd7d10fb5da12 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Mon, 27 Jan 2025 13:57:08 +0700
Subject: [PATCH] PeepholeOpt: Remove check for reg_sequence def of subregister
The verifier does not allow reg_sequence to have subregister defs,
even if undef.
---
llvm/lib/CodeGen/PeepholeOptimizer.cpp | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 2fc48209126acd..bf450e3af0deee 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1956,22 +1956,7 @@ ValueTrackerResult
ValueTracker::getNextSourceFromRegSequence() {
assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
"Invalid definition");
- if (Def->getOperand(DefIdx).getSubReg())
- // If we are composing subregs, bail out.
- // The case we are checking is Def.<subreg> = REG_SEQUENCE.
- // This should almost never happen as the SSA property is tracked at
- // the register level (as opposed to the subreg level).
- // I.e.,
- // Def.sub0 =
- // Def.sub1 =
- // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
- // Def. Thus, it must not be generated.
- // However, some code could theoretically generates a single
- // Def.sub0 (i.e, not defining the other subregs) and we would
- // have this case.
- // If we can ascertain (or force) that this never happens, we could
- // turn that into an assertion.
- return ValueTrackerResult();
+ assert(!Def->getOperand(DefIdx).getSubReg() && "illegal subregister def");
SmallVector<RegSubRegPairAndIdx, 8> RegSeqInputRegs;
if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
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