Author: Craig Topper Date: 2025-02-05T20:59:24-08:00 New Revision: c08c9f97f93b29842fbfd80791088abf42c753ca
URL: https://github.com/llvm/llvm-project/commit/c08c9f97f93b29842fbfd80791088abf42c753ca DIFF: https://github.com/llvm/llvm-project/commit/c08c9f97f93b29842fbfd80791088abf42c753ca.diff LOG: [RISCV] Use getSignedConstant for negative values. (#125903) The APInt constructor asserts if bits are set past the size of the APInt unless it is signed. This currently fails on RV32 because more than XLen bits are set. (cherry picked from commit 0d7ee520d3a9b8997adf8eaaa22b33db9659d94e) Added: Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 8d09e534b1858bc..8b5ee3e67ce637c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16297,7 +16297,7 @@ static SDValue performVP_REVERSECombine(SDNode *N, SelectionDAG &DAG, SDValue Temp2 = DAG.getNode(ISD::MUL, DL, XLenVT, Temp1, DAG.getConstant(ElemWidthByte, DL, XLenVT)); SDValue Base = DAG.getNode(ISD::ADD, DL, XLenVT, VPLoad->getBasePtr(), Temp2); - SDValue Stride = DAG.getConstant(-ElemWidthByte, DL, XLenVT); + SDValue Stride = DAG.getSignedConstant(-ElemWidthByte, DL, XLenVT); MachineFunction &MF = DAG.getMachineFunction(); MachinePointerInfo PtrInfo(VPLoad->getAddressSpace()); @@ -16358,7 +16358,7 @@ static SDValue performVP_STORECombine(SDNode *N, SelectionDAG &DAG, DAG.getConstant(ElemWidthByte, DL, XLenVT)); SDValue Base = DAG.getNode(ISD::ADD, DL, XLenVT, VPStore->getBasePtr(), Temp2); - SDValue Stride = DAG.getConstant(-ElemWidthByte, DL, XLenVT); + SDValue Stride = DAG.getSignedConstant(-ElemWidthByte, DL, XLenVT); MachineFunction &MF = DAG.getMachineFunction(); MachinePointerInfo PtrInfo(VPStore->getAddressSpace()); diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll b/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll index 50e26bd14107002..24d8e56fa17febc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s define <vscale x 2 x float> @test_reverse_load_combiner(<vscale x 2 x float>* %ptr, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll index 4896a1367935ac3..a2466c48b0ab7d9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s define void @test_store_reverse_combiner(<vscale x 2 x float> %val, <vscale x 2 x float>* %ptr, i32 zeroext %evl) { _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
