llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: None (CarolineConcatto) <details> <summary>Changes</summary> These features FEAT_FAMINMAX, FEAT_LUT and FEAT_FP8 depends on FEAT_NEON. Update dependency from FEAT_FP8DOT4 and FEAT_FP8DOT2. Now depends indirectly on FEAT_NEON through FEAT_FP8 --- Full diff: https://github.com/llvm/llvm-project/pull/126210.diff 3 Files Affected: - (modified) llvm/lib/Target/AArch64/AArch64Features.td (+5-5) - (modified) llvm/lib/Target/AArch64/AArch64Processors.td (+1-1) - (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+13-5) ``````````diff diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 20db70ee38572f2..d47dcfe92ff194f 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -473,13 +473,13 @@ def FeatureD128 : ExtensionWithMArch<"d128", "D128", //===----------------------------------------------------------------------===// def FeatureFAMINMAX: ExtensionWithMArch<"faminmax", "FAMINMAX", "FEAT_FAMINMAX", - "Enable FAMIN and FAMAX instructions">; + "Enable FAMIN and FAMAX instructions", [FeatureNEON]>; def FeatureLUT: ExtensionWithMArch<"lut", "LUT", "FEAT_LUT", - "Enable Lookup Table instructions">; + "Enable Lookup Table instructions", [FeatureNEON]>; def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8", "FEAT_FP8", - "Enable FP8 instructions", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>; + "Enable FP8 instructions", [FeatureNEON]>; def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA", "FEAT_FP8FMA", "Enable Armv9.5-A FP8 multiply-add instructions", [FeatureFP8]>; @@ -488,10 +488,10 @@ def FeatureSSVE_FP8FMA : ExtensionWithMArch<"ssve-fp8fma", "SSVE_FP8FMA", "FEAT_ "Enable SVE2 FP8 multiply-add instructions", [FeatureSME2, FeatureFP8]>; def FeatureFP8DOT4: ExtensionWithMArch<"fp8dot4", "FP8DOT4", "FEAT_FP8DOT4", - "Enable FP8 4-way dot instructions", [FeatureNEON, FeatureFP8]>; + "Enable FP8 4-way dot instructions", [FeatureFP8]>; def FeatureFP8DOT2: ExtensionWithMArch<"fp8dot2", "FP8DOT2", "FEAT_FP8DOT2", - "Enable FP8 2-way dot instructions", [FeatureNEON, FeatureFP8]>; + "Enable FP8 2-way dot instructions", [FeatureFP8]>; def FeatureSSVE_FP8DOT4 : ExtensionWithMArch<"ssve-fp8dot4", "SSVE_FP8DOT4", "FEAT_SSVE_FP8DOT4", "Enable SVE2 FP8 4-way dot product instructions", [FeatureSME2, FeatureFP8]>; diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 8a2c0442a0c0da4..d1d4986d1255077 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -868,7 +868,7 @@ def ProcessorFeatures { FeatureSSBS, FeatureLS64, FeatureCLRBHB, FeatureSPECRES2, FeatureSVEAES, FeatureSVE2SM4, FeatureSVE2SHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE, - FeatureMEC, FeatureFP8DOT2]; + FeatureMEC, FeatureFAMINMAX, FeatureFP8DOT2, FeatureLUT]; list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES, FeatureFullFP16, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM, FeatureFPARMv8]; diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index c594d38b50b22ed..fdf0b0fa2374487 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1814,7 +1814,7 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV9_6A, {"nofp", "fprcvt"}, {"fp-armv8", "fprcvt"}, {}}, {AArch64::ARMV9_6A, {"fprcvt", "nofp"}, {}, {"fp-armv8", "fprcvt"}}, - // simd -> {aes, sha2, sha3, sm4, f8f16mm, f8f32mm, fp8dot4, fp8dot2} + // simd -> {aes, sha2, sha3, sm4, f8f16mm, f8f32mm, faminmax, lut, fp8} {AArch64::ARMV8A, {"nosimd", "aes"}, {"neon", "aes"}, {}}, {AArch64::ARMV8A, {"aes", "nosimd"}, {}, {"neon", "aes"}}, {AArch64::ARMV8A, {"nosimd", "sha2"}, {"neon", "sha2"}, {}}, @@ -1827,10 +1827,18 @@ AArch64ExtensionDependenciesBaseArchTestParams {AArch64::ARMV9_6A, {"f8f16mm", "nosimd"}, {}, {"neon", "f8f16mm"}}, {AArch64::ARMV9_6A, {"nosimd", "f8f32mm"}, {"neon", "f8f32mm"}, {}}, {AArch64::ARMV9_6A, {"f8f32mm", "nosimd"}, {}, {"neon", "f8f32mm"}}, - {AArch64::ARMV9_6A, {"nosimd", "fp8dot4"}, {"neon", "fp8dot4"}, {}}, - {AArch64::ARMV9_6A, {"fp8dot4", "nosimd"}, {}, {"neon", "fp8dot4"}}, - {AArch64::ARMV9_6A, {"nosimd", "fp8dot2"}, {"neon", "fp8dot2"}, {}}, - {AArch64::ARMV9_6A, {"fp8dot2", "nosimd"}, {}, {"neon", "fp8dot2"}}, + {AArch64::ARMV9_6A, {"faminmax", "nosimd"}, {}, {"neon", "faminmax"}}, + {AArch64::ARMV9_6A, {"nosimd", "faminmax"}, {"neon", "faminmax"}, {}}, + {AArch64::ARMV9_6A, {"lut", "nosimd"}, {}, {"neon", "lut"}}, + {AArch64::ARMV9_6A, {"nosimd", "lut"}, {"neon", "lut"}, {}}, + {AArch64::ARMV9_6A, {"fp8", "nosimd"}, {}, {"neon", "fp8"}}, + {AArch64::ARMV9_6A, {"nosimd", "fp8"}, {"neon", "fp8"}, {}}, + + // fp8 -> {fp8dot4, fp8dot2} + {AArch64::ARMV9_6A, {"nofp8", "fp8dot4"}, {"fp8", "fp8dot4"}, {}}, + {AArch64::ARMV9_6A, {"fp8dot4", "nofp8"}, {}, {"fp8", "fp8dot4"}}, + {AArch64::ARMV9_6A, {"nofp8", "fp8dot2"}, {"fp8", "fp8dot2"}, {}}, + {AArch64::ARMV9_6A, {"fp8dot2", "nofp8"}, {}, {"fp8", "fp8dot2"}}, // simd -> {rdm, dotprod, fcma} {AArch64::ARMV8A, {"nosimd", "rdm"}, {"neon", "rdm"}, {}}, `````````` </details> https://github.com/llvm/llvm-project/pull/126210 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
