https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126878
>From 05da561320a9ce66e13fe1b952b3214371150563 Mon Sep 17 00:00:00 2001
From: Fabian Ritter <fabian.rit...@amd.com>
Date: Wed, 12 Feb 2025 04:13:18 -0500
Subject: [PATCH] [AMDGPU] Remove FeatureForceStoreSC0SC1
This was only used for gfx940 and gfx941, which have since been removed.
For SWDEV-512631
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 6 ------
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 ---
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 20 --------------------
3 files changed, 29 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 3aabca49b249e..effc8d2ed6b49 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1040,12 +1040,6 @@ def FeatureVALUTransUseHazard :
SubtargetFeature<"valu-trans-use-hazard",
"Hazard when TRANS instructions are closely followed by a use of the result"
>;
-def FeatureForceStoreSC0SC1 : SubtargetFeature<"force-store-sc0-sc1",
- "HasForceStoreSC0SC1",
- "true",
- "Has SC0 and SC1 on stores"
->;
-
def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
"HasSALUFloatInsts",
"true",
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index f7c5c472c93a5..6664a70572ded 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -246,7 +246,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasMADIntraFwdBug = false;
bool HasVOPDInsts = false;
bool HasVALUTransUseHazard = false;
- bool HasForceStoreSC0SC1 = false;
bool HasRequiredExportPriority = false;
bool HasVmemWriteVgprInOrder = false;
bool HasAshrPkInsts = false;
@@ -1264,8 +1263,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasCvtScaleForwardingHazard() const { return GFX950Insts; }
- bool hasForceStoreSC0SC1() const { return HasForceStoreSC0SC1; }
-
bool requiresCodeObjectV6() const { return RequiresCOV6; }
bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; }
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 79fb36acc0ea7..34953f9c08db7 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -359,11 +359,6 @@ class SICacheControl {
/// Virtual destructor to allow derivations to be deleted.
virtual ~SICacheControl() = default;
-
- virtual bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
- MachineBasicBlock::iterator &MI) const {
- return false;
- }
};
class SIGfx6CacheControl : public SICacheControl {
@@ -517,20 +512,6 @@ class SIGfx940CacheControl : public SIGfx90ACacheControl {
bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, bool
IsCrossAddrSpaceOrdering,
Position Pos) const override;
-
- bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
- MachineBasicBlock::iterator &MI) const override {
- bool Changed = false;
- if (ST.hasForceStoreSC0SC1() &&
- (MOI.getInstrAddrSpace() & (SIAtomicAddrSpace::SCRATCH |
- SIAtomicAddrSpace::GLOBAL |
- SIAtomicAddrSpace::OTHER)) !=
- SIAtomicAddrSpace::NONE) {
- Changed |= enableSC0Bit(MI);
- Changed |= enableSC1Bit(MI);
- }
- return Changed;
- }
};
class SIGfx10CacheControl : public SIGfx7CacheControl {
@@ -2820,7 +2801,6 @@ bool
SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
Changed |= expandLoad(*MOI, MI);
else if (const auto &MOI = MOA.getStoreInfo(MI)) {
Changed |= expandStore(*MOI, MI);
- Changed |= CC->tryForceStoreSC0SC1(*MOI, MI);
} else if (const auto &MOI = MOA.getAtomicFenceInfo(MI))
Changed |= expandAtomicFence(*MOI, MI);
else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI))
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