https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/128717
>From c99be9188631e5f5a21a0041d85385bd05659a3d Mon Sep 17 00:00:00 2001 From: Yingwei Zheng <dtcxzyw2...@gmail.com> Date: Tue, 25 Feb 2025 22:03:17 +0800 Subject: [PATCH] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (#128618) f80 is not a valid IEEE floating-point type. Closes https://github.com/llvm/llvm-project/issues/128528. (cherry picked from commit 44d1dbd24c20a0ee93063dcf44d68e2b8f0bf77c) --- llvm/include/llvm/ADT/APFloat.h | 1 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 +++-- llvm/lib/Support/APFloat.cpp | 5 ++++ .../X86/fold-int-pow2-with-fmul-or-fdiv.ll | 28 +++++++++++++++++++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h index 9792749230cbf..3bff205e7aa9e 100644 --- a/llvm/include/llvm/ADT/APFloat.h +++ b/llvm/include/llvm/ADT/APFloat.h @@ -353,6 +353,7 @@ struct APFloatBase { static bool semanticsHasSignedRepr(const fltSemantics &); static bool semanticsHasInf(const fltSemantics &); static bool semanticsHasNaN(const fltSemantics &); + static bool isIEEELikeFP(const fltSemantics &); // Returns true if any number described by \p Src can be precisely represented // by a normal (not subnormal) value in \p Dst. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 1e023d4f76b2c..9d04568483677 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -17283,6 +17283,9 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { // prefer it. SDValue DAGCombiner::combineFMulOrFDivWithIntPow2(SDNode *N) { EVT VT = N->getValueType(0); + if (!APFloat::isIEEELikeFP(VT.getFltSemantics())) + return SDValue(); + SDValue ConstOp, Pow2Op; std::optional<int> Mantissa; @@ -17309,8 +17312,8 @@ SDValue DAGCombiner::combineFMulOrFDivWithIntPow2(SDNode *N) { const APFloat &APF = CFP->getValueAPF(); - // Make sure we have normal/ieee constant. - if (!APF.isNormal() || !APF.isIEEE()) + // Make sure we have normal constant. + if (!APF.isNormal()) return false; // Make sure the floats exponent is within the bounds that this transform diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp index b0d92ae37fe8f..cbee7f48b8773 100644 --- a/llvm/lib/Support/APFloat.cpp +++ b/llvm/lib/Support/APFloat.cpp @@ -353,6 +353,11 @@ bool APFloatBase::semanticsHasNaN(const fltSemantics &semantics) { return semantics.nonFiniteBehavior != fltNonfiniteBehavior::FiniteOnly; } +bool APFloatBase::isIEEELikeFP(const fltSemantics &semantics) { + // Keep in sync with Type::isIEEELikeFPTy + return SemanticsToEnum(semantics) <= S_IEEEquad; +} + bool APFloatBase::isRepresentableAsNormalIn(const fltSemantics &Src, const fltSemantics &Dst) { // Exponent range must be larger. diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll index 2163121410553..15a9cbecd808a 100644 --- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll +++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll @@ -1662,3 +1662,31 @@ define float @fdiv_pow_shl_cnt32_okay(i32 %cnt) nounwind { %mul = fdiv float 0x3a20000000000000, %conv ret float %mul } + +define x86_fp80 @pr128528(i1 %cond) { +; CHECK-SSE-LABEL: pr128528: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: testb $1, %dil +; CHECK-SSE-NEXT: movl $8, %eax +; CHECK-SSE-NEXT: movl $1, %ecx +; CHECK-SSE-NEXT: cmovnel %eax, %ecx +; CHECK-SSE-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: fildl -{{[0-9]+}}(%rsp) +; CHECK-SSE-NEXT: fmull {{\.?LCPI[0-9]+_[0-9]+}}(%rip) +; CHECK-SSE-NEXT: retq +; +; CHECK-AVX-LABEL: pr128528: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: testb $1, %dil +; CHECK-AVX-NEXT: movl $8, %eax +; CHECK-AVX-NEXT: movl $1, %ecx +; CHECK-AVX-NEXT: cmovnel %eax, %ecx +; CHECK-AVX-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) +; CHECK-AVX-NEXT: fildl -{{[0-9]+}}(%rsp) +; CHECK-AVX-NEXT: fmull {{\.?LCPI[0-9]+_[0-9]+}}(%rip) +; CHECK-AVX-NEXT: retq + %sub9 = select i1 %cond, i32 8, i32 1 + %conv = uitofp i32 %sub9 to x86_fp80 + %mul = fmul x86_fp80 %conv, 0xK4007D055555555555800 + ret x86_fp80 %mul +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
