[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

[Carl Ritson via llvm-branch-commits]

================
@@ -552,6 +552,7 @@ enum Id { // HwRegCode, (6) [5:0]
 
 enum Offset : unsigned { // Offset, (5) [10:6]
   OFFSET_MEM_VIOL = 8,
+  OFFSET_ME_ID = 8,
----------------
perlfu wrote:

It's slightly confusing that this enumeration of offsets applies to multiple 
registers.
Perhaps comment which register this is for?
e.g. `OFFSET_ME_ID = 8, // in HW_ID2`

https://github.com/llvm/llvm-project/pull/130055
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