https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130564
>From b1194b992d8aa79a000766e441af31f17aa05c07 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Mon, 10 Mar 2025 06:14:27 +0000
Subject: [PATCH 1/3] [CodeGen][NPM] Port VirtRegRewriter to NPM
Not sure why this is squished into VirtRegMap.h
---
llvm/include/llvm/CodeGen/VirtRegMap.h | 13 +++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 7 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/VirtRegMap.cpp | 84 +++++++++++++++----
llvm/lib/Passes/PassBuilder.cpp | 13 +++
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 +-
.../AMDGPU/alloc-aligned-tuples-gfx90a.mir | 2 +
.../CodeGen/AMDGPU/fold-restore-undef-use.mir | 2 +
.../greedy-remark-crash-unassigned-reg.mir | 4 +
llvm/test/CodeGen/X86/pr30821.mir | 1 +
12 files changed, 115 insertions(+), 22 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h
b/llvm/include/llvm/CodeGen/VirtRegMap.h
index c9e405e1981d9..e74131545f277 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -235,6 +235,19 @@ class VirtRegMapPrinterPass : public
PassInfoMixin<VirtRegMapPrinterPass> {
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
+
+class VirtRegRewriterPass : public PassInfoMixin<VirtRegRewriterPass> {
+ bool ClearVirtRegs = true;
+public:
+ VirtRegRewriterPass(bool ClearVirtRegs = true) :
ClearVirtRegs(ClearVirtRegs) {}
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ static bool isRequired() { return true; }
+
+ void printPipeline(raw_ostream &OS, function_ref<StringRef(StringRef)>)
const;
+};
+
} // end llvm namespace
#endif // LLVM_CODEGEN_VIRTREGMAP_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index a05e876806ab5..fb33b7a985ba5 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -316,7 +316,7 @@ void
initializeUnreachableBlockElimLegacyPassPass(PassRegistry &);
void initializeUnreachableMachineBlockElimPass(PassRegistry &);
void initializeVerifierLegacyPassPass(PassRegistry &);
void initializeVirtRegMapWrapperLegacyPass(PassRegistry &);
-void initializeVirtRegRewriterPass(PassRegistry &);
+void initializeVirtRegRewriterLegacyPass(PassRegistry &);
void initializeWasmEHPreparePass(PassRegistry &);
void initializeWinEHPreparePass(PassRegistry &);
void initializeWriteBitcodePassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 25899d04dc664..98de12a05f1f5 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -82,6 +82,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TwoAddressInstructionPass.h"
#include "llvm/CodeGen/UnreachableBlockElim.h"
+#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/CodeGen/WasmEHPrepare.h"
#include "llvm/CodeGen/WinEHPrepare.h"
#include "llvm/IR/PassManager.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index f99a5f2c74bf3..dce2dc3a29abd 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -216,6 +216,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "virt-reg-rewriter", "VirtRegRewriterPass",
+ [](bool ClearVirtRegs) { return VirtRegRewriterPass(ClearVirtRegs); },
+ parseVirtRegRewriterPassOptions, "no-clear-vregs;clear-vregs")
+
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved
from
@@ -287,6 +293,5 @@ DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass)
DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass)
DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass)
DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass)
-DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass)
DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass)
#undef DUMMY_MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index beb7fb284a376..1a9385f8608de 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -141,7 +141,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeUnreachableBlockElimLegacyPassPass(Registry);
initializeUnreachableMachineBlockElimPass(Registry);
initializeVirtRegMapWrapperLegacyPass(Registry);
- initializeVirtRegRewriterPass(Registry);
+ initializeVirtRegRewriterLegacyPass(Registry);
initializeWasmEHPreparePass(Registry);
initializeWinEHPreparePass(Registry);
initializeXRayInstrumentationPass(Registry);
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 0fc3e5d9a3052..218b52ab7add2 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
@@ -197,7 +198,7 @@ VirtRegMap VirtRegMapAnalysis::run(MachineFunction &MF,
//
namespace {
-class VirtRegRewriter : public MachineFunctionPass {
+class VirtRegRewriter {
MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
const TargetInstrInfo *TII = nullptr;
@@ -223,9 +224,22 @@ class VirtRegRewriter : public MachineFunctionPass {
public:
static char ID;
- VirtRegRewriter(bool ClearVirtRegs_ = true) :
- MachineFunctionPass(ID),
- ClearVirtRegs(ClearVirtRegs_) {}
+ VirtRegRewriter(bool ClearVirtRegs, SlotIndexes *Indexes, LiveIntervals *LIS,
+ LiveRegMatrix *LRM, VirtRegMap *VRM,
+ LiveDebugVariables *DebugVars)
+ : Indexes(Indexes), LIS(LIS), LRM(LRM), VRM(VRM), DebugVars(DebugVars),
+ ClearVirtRegs(ClearVirtRegs) {}
+
+ bool run(MachineFunction&);
+
+};
+
+class VirtRegRewriterLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+ bool ClearVirtRegs;
+ VirtRegRewriterLegacy(bool ClearVirtRegs = true) :
+ MachineFunctionPass(ID), ClearVirtRegs(ClearVirtRegs) {}
void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -243,11 +257,11 @@ class VirtRegRewriter : public MachineFunctionPass {
} // end anonymous namespace
-char VirtRegRewriter::ID = 0;
+char VirtRegRewriterLegacy::ID = 0;
-char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
+char &llvm::VirtRegRewriterID = VirtRegRewriterLegacy::ID;
-INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_BEGIN(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
@@ -255,10 +269,10 @@
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
-INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_END(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
-void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
+void VirtRegRewriterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
@@ -276,16 +290,47 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU)
const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
+bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
+ VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ LiveRegMatrix &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ SlotIndexes &Indexes = getAnalysis<SlotIndexesWrapperPass>().getSI();
+ LiveDebugVariables &DebugVars =
+ getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ return R.run(MF);
+}
+
+PreservedAnalyses VirtRegRewriterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ VirtRegMap &VRM = MFAM.getResult<VirtRegMapAnalysis>(MF);
+ LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ LiveRegMatrix &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ SlotIndexes &Indexes = MFAM.getResult<SlotIndexesAnalysis>(MF);
+ LiveDebugVariables &DebugVars =
MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ if (!R.run(MF))
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ // LiveDebugVariables is preserved by default, so clear it
+ // if this VRegRewriter is the last one in the pipeline.
+ if (ClearVirtRegs)
+ PA.abandon<LiveDebugVariablesAnalysis>();
+ return PA;
+}
+
+bool VirtRegRewriter::run(MachineFunction &fn) {
MF = &fn;
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
MRI = &MF->getRegInfo();
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
- VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
- DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
<< "********** Function: " << MF->getName() << '\n');
LLVM_DEBUG(VRM->dump());
@@ -726,6 +771,13 @@ void VirtRegRewriter::rewrite() {
RewriteRegs.clear();
}
+void VirtRegRewriterPass::printPipeline(raw_ostream &OS,
function_ref<StringRef(StringRef)>) const {
+ OS << "virt-reg-rewriter<";
+ if (!ClearVirtRegs)
+ OS << "no-";
+ OS << "clear-vregs>";
+}
+
FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
- return new VirtRegRewriter(ClearVirtRegs);
+ return new VirtRegRewriterLegacy(ClearVirtRegs);
}
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 8080059f0bb03..f86a4c6adb8f1 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1439,6 +1439,19 @@ Expected<bool> parseMachineSinkingPassOptions(StringRef
Params) {
"MachineSinkingPass");
}
+Expected<bool> parseVirtRegRewriterPassOptions(StringRef Params) {
+ bool ClearVirtRegs = true;
+ if (!Params.empty()) {
+ ClearVirtRegs = !Params.consume_front("no-");
+ if (Params != "clear-vregs")
+ return make_error<StringError>(
+ formatv("invalid VirtRegRewriter pass parameter '{0}' ", Params)
+ .str(),
+ inconvertibleErrorCode());
+ }
+ return ClearVirtRegs;
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1167465444f12..044efcff11c78 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -2238,7 +2238,7 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// many things rely on the use lists of the physical registers, such as the
// verifier. This is only necessary with allocators which use LiveIntervals,
// since FastRegAlloc does the replacements itself.
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// At this point, the sgpr-regalloc has been done and it is good to have the
// stack slot coloring to try to optimize the SGPR spill stack indices before
@@ -2254,14 +2254,14 @@ Error
AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// For allocating other wwm register operands.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::WWM);
addPass(SILowerWWMCopiesPass());
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// TODO: addPass(AMDGPUReserveWWMRegsPass());
// For allocating per-thread VGPRs.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::VGPR);
// TODO: addPreRewrite();
- addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(true));
// TODO: addPass(AMDGPUMarkLastScratchLoadPass());
return Error::success();
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
index c42b570b40812..8ae90bde0c8ce 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
@@ -1,4 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0
-stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck
--check-prefixes=GCN,GFX90A %s
+
+# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0
-stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck
--check-prefixes=GCN,GFX90A %s
# Using the unaligned vector tuples are OK as long as they aren't used
# in a real instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
index 5ef8a94eeaa7c..f9af0a03e51d0 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stress-regalloc=4
-verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 %s -o - |
FileCheck %s
+# RUN: llc -enable-new-pm -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a
-stress-regalloc=4 -verify-regalloc
-passes="greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>" %s -o - | FileCheck %s
+
# Check that we don't generate *** Bad machine code: Instruction loads
# from dead spill slot ***
diff --git a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
index 374617c93ce4d..8754547a23a68 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
@@ -2,6 +2,10 @@
# RUN: -start-before=greedy,0 -stop-after=virtregrewriter,0
-pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
# RUN: FileCheck %s < %t.yaml
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 \
+# RUN: -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>'
-pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
+# RUN: FileCheck %s < %t.yaml
+
# CHECK: Name: SpillReloadCopies
# CHECK-NEXT: Function: func
# CHECK-NEXT: Args:
diff --git a/llvm/test/CodeGen/X86/pr30821.mir
b/llvm/test/CodeGen/X86/pr30821.mir
index 992ef8bbe55f0..dccb49277b519 100644
--- a/llvm/test/CodeGen/X86/pr30821.mir
+++ b/llvm/test/CodeGen/X86/pr30821.mir
@@ -1,4 +1,5 @@
# RUN: llc -x mir < %s -run-pass=greedy,virtregrewriter,stack-slot-coloring |
FileCheck %s
+# RUN: llc -x mir < %s -passes=greedy,virt-reg-rewriter,stack-slot-coloring |
FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
>From 83f4fa7ac9e43baed20850992f2073da381f3ae1 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Mon, 10 Mar 2025 10:28:13 +0000
Subject: [PATCH 2/3] clang format
---
llvm/include/llvm/CodeGen/VirtRegMap.h | 4 +++-
llvm/lib/CodeGen/VirtRegMap.cpp | 19 ++++++++++---------
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h
b/llvm/include/llvm/CodeGen/VirtRegMap.h
index e74131545f277..f5fba0d65401e 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -238,8 +238,10 @@ class VirtRegMapPrinterPass : public
PassInfoMixin<VirtRegMapPrinterPass> {
class VirtRegRewriterPass : public PassInfoMixin<VirtRegRewriterPass> {
bool ClearVirtRegs = true;
+
public:
- VirtRegRewriterPass(bool ClearVirtRegs = true) :
ClearVirtRegs(ClearVirtRegs) {}
+ VirtRegRewriterPass(bool ClearVirtRegs = true)
+ : ClearVirtRegs(ClearVirtRegs) {}
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 218b52ab7add2..a00f6bc0bf3ae 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -29,7 +29,6 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
@@ -230,16 +229,15 @@ class VirtRegRewriter {
: Indexes(Indexes), LIS(LIS), LRM(LRM), VRM(VRM), DebugVars(DebugVars),
ClearVirtRegs(ClearVirtRegs) {}
- bool run(MachineFunction&);
-
+ bool run(MachineFunction &);
};
class VirtRegRewriterLegacy : public MachineFunctionPass {
public:
static char ID;
bool ClearVirtRegs;
- VirtRegRewriterLegacy(bool ClearVirtRegs = true) :
- MachineFunctionPass(ID), ClearVirtRegs(ClearVirtRegs) {}
+ VirtRegRewriterLegacy(bool ClearVirtRegs = true)
+ : MachineFunctionPass(ID), ClearVirtRegs(ClearVirtRegs) {}
void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -302,13 +300,15 @@ bool
VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
return R.run(MF);
}
-PreservedAnalyses VirtRegRewriterPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
+PreservedAnalyses
+VirtRegRewriterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
VirtRegMap &VRM = MFAM.getResult<VirtRegMapAnalysis>(MF);
LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
LiveRegMatrix &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);
SlotIndexes &Indexes = MFAM.getResult<SlotIndexesAnalysis>(MF);
- LiveDebugVariables &DebugVars =
MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+ LiveDebugVariables &DebugVars =
+ MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
if (!R.run(MF))
@@ -771,7 +771,8 @@ void VirtRegRewriter::rewrite() {
RewriteRegs.clear();
}
-void VirtRegRewriterPass::printPipeline(raw_ostream &OS,
function_ref<StringRef(StringRef)>) const {
+void VirtRegRewriterPass::printPipeline(
+ raw_ostream &OS, function_ref<StringRef(StringRef)>) const {
OS << "virt-reg-rewriter<";
if (!ClearVirtRegs)
OS << "no-";
>From 65cd44317a450b6b0f753ab7cedd7df5db310f54 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Tue, 11 Mar 2025 10:06:55 +0000
Subject: [PATCH 3/3] AS
---
llvm/lib/CodeGen/VirtRegMap.cpp | 6 +++---
llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index a00f6bc0bf3ae..60859fdcd59cf 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -313,6 +313,7 @@ VirtRegRewriterPass::run(MachineFunction &MF,
VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
if (!R.run(MF))
return PreservedAnalyses::all();
+
auto PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
PA.preserve<LiveIntervalsAnalysis>();
@@ -773,10 +774,9 @@ void VirtRegRewriter::rewrite() {
void VirtRegRewriterPass::printPipeline(
raw_ostream &OS, function_ref<StringRef(StringRef)>) const {
- OS << "virt-reg-rewriter<";
+ OS << "virt-reg-rewriter";
if (!ClearVirtRegs)
- OS << "no-";
- OS << "clear-vregs>";
+ OS << "<no-clear-vregs>";
}
FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
index 8ae90bde0c8ce..98c0eca4345c6 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
@@ -1,6 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0
-stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck
--check-prefixes=GCN,GFX90A %s
-# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0
-stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck
--check-prefixes=GCN,GFX90A %s
+# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0
-stop-after=virt-reg-rewriter,2 -o - %s | FileCheck --check-prefixes=GCN,GFX90A
%s
# Using the unaligned vector tuples are OK as long as they aren't used
# in a real instruction.
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
