https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/131255
>From 9eeb3a6aa1ff43ea4b60320ffb532db1b1a772b3 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <matthew.arsena...@amd.com> Date: Thu, 13 Mar 2025 16:27:08 +0700 Subject: [PATCH] AMDGPU: Switch a test with only function label checks to generated I suspect the first function at least is not usefully testing the original failure. --- .../CodeGen/AMDGPU/subreg-coalescer-crash.ll | 37 ++++++++++++++++--- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll index 19c43fa22271b..a0ac6c1b28449 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll @@ -1,8 +1,13 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn -mcpu=tahiti -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s +; RUN: llc -mtriple=amdgcn -mcpu=tonga -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s -; GCN-LABEL:{{^}}row_filter_C1_D0: define amdgpu_kernel void @row_filter_C1_D0() #0 { +; GCN-LABEL: row_filter_C1_D0: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_cbranch_scc1 .LBB0_2 +; GCN-NEXT: ; %bb.1: ; %do.body.preheader +; GCN-NEXT: .LBB0_2: ; %for.inc.1 entry: br i1 undef, label %for.inc.1, label %do.body.preheader @@ -40,9 +45,28 @@ for.inc.1: ; preds = %do.body.1562.prehea unreachable } -; GCN-LABEL: {{^}}foo: -; GCN: s_endpgm define amdgpu_ps void @foo() #0 { +; GCN-LABEL: foo: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_mov_b64 s[0:1], -1 +; GCN-NEXT: s_cbranch_scc0 .LBB1_2 +; GCN-NEXT: ; %bb.1: ; %bb24 +; GCN-NEXT: s_mov_b64 s[0:1], 0 +; GCN-NEXT: .LBB1_2: ; %Flow1 +; GCN-NEXT: s_and_b64 vcc, exec, s[0:1] +; GCN-NEXT: s_cbranch_vccz .LBB1_4 +; GCN-NEXT: ; %bb.3: ; %bb9 +; GCN-NEXT: image_sample v[0:1], v0, s[0:7], s[0:3] dmask:0xa +; GCN-NEXT: s_branch .LBB1_5 +; GCN-NEXT: .LBB1_4: +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_mov_b32_e32 v0, v1 +; GCN-NEXT: .LBB1_5: ; %bb14 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 0x41280000, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x41380000, v1 +; GCN-NEXT: exp mrt0 v1, v0, v0, v0 done vm +; GCN-NEXT: s_endpgm bb: br i1 undef, label %bb2, label %bb1 @@ -101,3 +125,6 @@ declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32> attributes #0 = { nounwind } attributes #1 = { nounwind readonly } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX6: {{.*}} +; GFX8: {{.*}} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits