================
@@ -489,22 +489,61 @@ RegBankLegalizeRules::RegBankLegalizeRules(const
GCNSubtarget &_ST,
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}});
addRulesForGOpcs({G_ANYEXT})
+ .Any({{UniS16, S1}, {{None}, {None}}}) // should be combined away
.Any({{UniS32, S1}, {{None}, {None}}}) // should be combined away
- .Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}});
+ .Any({{UniS64, S1}, {{None}, {None}}}) // should be combined away
+ .Any({{{DivS16, S1}}, {{Vgpr16}, {Vcc}, VccExtToSel}})
+ .Any({{{DivS32, S1}}, {{Vgpr32}, {Vcc}, VccExtToSel}})
+ .Any({{{DivS64, S1}}, {{Vgpr64}, {Vcc}, VccExtToSel}})
+ .Any({{UniS64, S32}, {{Sgpr64}, {Sgpr32}, Ext32To64}})
----------------
petar-avramovic wrote:
Quick explanation for now:
.Any({**{DivS32, S1}**, {{Vgpr32}, {Vcc}, VccExtToSel}}) is list for predicate
checks uniform/divergent and types of operands. Usually one is enough (just
dst) but here we check for divergent S32 dst and S1 source
there is a place for c++ check here (see loads)
.Any({{DivS32, S1}, {**{Vgpr32}**, {Vcc}, VccExtToSel}}) list of which register
bank to apply on dst registers (check RegBankLegalizeHelper for details)
.Any({{DivS32, S1}, {{Vgpr32}, **{Vcc}**, VccExtToSel}}) list of which register
bank to apply on source registers
.Any({{DivS32, S1}, {{Vgpr32}, {Vcc}, **VccExtToSel**}}) ID of more complicated
lowering method, for example this one is transforming G_ANYEXT to G_SELECT
https://github.com/llvm/llvm-project/pull/132383
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