https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/132138
Backport 9c65e6ac115a
Requested by: @androm3da
>From e09e2480046740628cc28055010aef1ab05e5aff Mon Sep 17 00:00:00 2001
From: Abinaya Saravanan <quic_asara...@quicinc.com>
Date: Thu, 13 Mar 2025 03:28:26 +0530
Subject: [PATCH] [HEXAGON] Add support to lower "FREEZE a half(f16)"
instruction on Hexagon and fix the isel-buildvector-v2f16.ll assertion
(#130977)
(cherry picked from commit 9c65e6ac115a7d8566c874537791125c3ace7c1a)
---
llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 +
.../Target/Hexagon/HexagonISelLoweringHVX.cpp | 22 +++++-----
llvm/test/CodeGen/Hexagon/fp16-promote.ll | 44 +++++++++++++++++++
3 files changed, 56 insertions(+), 11 deletions(-)
create mode 100644 llvm/test/CodeGen/Hexagon/fp16-promote.ll
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index aaa9c65c1e07e..4df88b3a8abd7 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -362,6 +362,7 @@ class HexagonTargetLowering : public TargetLowering {
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
return AtomicExpansionKind::LLSC;
}
+ bool softPromoteHalfType() const override { return true; }
private:
void initializeHVXLowering();
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 1a19e81a68f08..a7eb20a3e5ff9 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1618,17 +1618,6 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op,
SelectionDAG &DAG)
for (unsigned i = 0; i != Size; ++i)
Ops.push_back(Op.getOperand(i));
- // First, split the BUILD_VECTOR for vector pairs. We could generate
- // some pairs directly (via splat), but splats should be generated
- // by the combiner prior to getting here.
- if (VecTy.getSizeInBits() == 16*Subtarget.getVectorLength()) {
- ArrayRef<SDValue> A(Ops);
- MVT SingleTy = typeSplit(VecTy).first;
- SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG);
- SDValue V1 = buildHvxVectorReg(A.drop_front(Size/2), dl, SingleTy, DAG);
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
- }
-
if (VecTy.getVectorElementType() == MVT::i1)
return buildHvxVectorPred(Ops, dl, VecTy, DAG);
@@ -1645,6 +1634,17 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op,
SelectionDAG &DAG)
return DAG.getBitcast(tyVector(VecTy, MVT::f16), T0);
}
+ // First, split the BUILD_VECTOR for vector pairs. We could generate
+ // some pairs directly (via splat), but splats should be generated
+ // by the combiner prior to getting here.
+ if (VecTy.getSizeInBits() == 16 * Subtarget.getVectorLength()) {
+ ArrayRef<SDValue> A(Ops);
+ MVT SingleTy = typeSplit(VecTy).first;
+ SDValue V0 = buildHvxVectorReg(A.take_front(Size / 2), dl, SingleTy, DAG);
+ SDValue V1 = buildHvxVectorReg(A.drop_front(Size / 2), dl, SingleTy, DAG);
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
+ }
+
return buildHvxVectorReg(Ops, dl, VecTy, DAG);
}
diff --git a/llvm/test/CodeGen/Hexagon/fp16-promote.ll
b/llvm/test/CodeGen/Hexagon/fp16-promote.ll
new file mode 100644
index 0000000000000..1ef0a133ce30a
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fp16-promote.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define half @freeze_half_undef() nounwind {
+; CHECK-LABEL: freeze_half_undef:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: call __truncsfhf2
+; CHECK-NEXT: r0 = #0
+; CHECK-NEXT: allocframe(#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: call __extendhfsf2
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: call __truncsfhf2
+; CHECK-NEXT: r0 = sfadd(r0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT: }
+ %y1 = freeze half undef
+ %t1 = fadd half %y1, %y1
+ ret half %t1
+}
+
+define half @freeze_half_poison(half %maybe.poison) {
+; CHECK-LABEL: freeze_half_poison:
+; CHECK: // %bb.0:
+; CHECK: {
+; CHECK-NEXT: call __extendhfsf2
+; CHECK-NEXT: allocframe(r29,#0):raw
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: call __truncsfhf2
+; CHECK-NEXT: r0 = sfadd(r0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT: }
+ %y1 = freeze half %maybe.poison
+ %t1 = fadd half %y1, %y1
+ ret half %t1
+}
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