================ @@ -0,0 +1,55 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS2 +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis2 -show-encoding | FileCheck %s --check-prefixes=VIS2 + +!! VIS 2 instructions. + +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: bmask %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x03,0x29] +bmask %o0, %o1, %o2 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: bshuffle %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x09,0x82] +bshuffle %f0, %f2, %f4 + +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 0 ! encoding: [0x81,0xb0,0x10,0x20] +siam 0 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 1 ! encoding: [0x81,0xb0,0x10,0x21] +siam 1 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 2 ! encoding: [0x81,0xb0,0x10,0x22] +siam 2 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 3 ! encoding: [0x81,0xb0,0x10,0x23] +siam 3 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 4 ! encoding: [0x81,0xb0,0x10,0x24] +siam 4 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 5 ! encoding: [0x81,0xb0,0x10,0x25] +siam 5 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 6 ! encoding: [0x81,0xb0,0x10,0x26] +siam 6 +! NO-VIS2: error: instruction requires a CPU feature not currently enabled +! VIS2: siam 7 ! encoding: [0x81,0xb0,0x10,0x27] +siam 7 ---------------- s-barannikov wrote:
`siam -1` / `siam 8` should be rejected, but it looks like immediates in other instructions are not checked at all. Add a FIXME to operand descriptions that they should have AsmOperandClass? https://github.com/llvm/llvm-project/pull/130967 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
