llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/135716.diff 3 Files Affected: - (modified) llvm/lib/Target/Sparc/SparcISelLowering.cpp (+8-4) - (modified) llvm/lib/Target/Sparc/SparcInstrVIS.td (+13-6) - (added) llvm/test/CodeGen/SPARC/bitcast.ll (+139) ``````````diff diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index c34a55bb2881b..98fcaba86fee0 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1704,8 +1704,10 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand); - setOperationAction(ISD::BITCAST, MVT::f32, Expand); - setOperationAction(ISD::BITCAST, MVT::i32, Expand); + setOperationAction(ISD::BITCAST, MVT::f32, + Subtarget->isVIS3() ? Legal : Expand); + setOperationAction(ISD::BITCAST, MVT::i32, + Subtarget->isVIS3() ? Legal : Expand); // Sparc has no select or setcc: expand to SELECT_CC. setOperationAction(ISD::SELECT, MVT::i32, Expand); @@ -1743,8 +1745,10 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, } if (Subtarget->is64Bit()) { - setOperationAction(ISD::BITCAST, MVT::f64, Expand); - setOperationAction(ISD::BITCAST, MVT::i64, Expand); + setOperationAction(ISD::BITCAST, MVT::f64, + Subtarget->isVIS3() ? Legal : Expand); + setOperationAction(ISD::BITCAST, MVT::i64, + Subtarget->isVIS3() ? Legal : Expand); setOperationAction(ISD::SELECT, MVT::i64, Expand); setOperationAction(ISD::SETCC, MVT::i64, Expand); setOperationAction(ISD::BR_CC, MVT::i64, Custom); diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td index 241d6bc11e963..b806f0c413899 100644 --- a/llvm/lib/Target/Sparc/SparcInstrVIS.td +++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td @@ -259,14 +259,14 @@ def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd), (ins I64Regs:$rs2), "lzcnt $rs2, $rd">; let rs1 = 0 in { -def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd), - (ins DFPRegs:$rs2), "movstosw $rs2, $rd">; -def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd), - (ins DFPRegs:$rs2), "movstouw $rs2, $rd">; +def MOVSTOSW : VISInstFormat<0b100010011, (outs IntRegs:$rd), + (ins FPRegs:$rs2), "movstosw $rs2, $rd">; +def MOVSTOUW : VISInstFormat<0b100010001, (outs IntRegs:$rd), + (ins FPRegs:$rs2), "movstouw $rs2, $rd">; def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd), (ins DFPRegs:$rs2), "movdtox $rs2, $rd">; -def MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd), - (ins I64Regs:$rs2), "movwtos $rs2, $rd">; +def MOVWTOS : VISInstFormat<0b100011001, (outs FPRegs:$rd), + (ins IntRegs:$rs2), "movwtos $rs2, $rd">; def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd), (ins I64Regs:$rs2), "movxtod $rs2, $rd">; } @@ -309,4 +309,11 @@ def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>; // The zero extension will leave us with 32 extra leading zeros, // so we need to compensate for it. def : Pat<(i32 (ctlz i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>; + +def : Pat<(i32 (bitconvert f32:$src)), (MOVSTOUW $src)>; +def : Pat<(i64 (zext (i32 (bitconvert f32:$src)))), (MOVSTOUW $src)>; +def : Pat<(i64 (sext (i32 (bitconvert f32:$src)))), (MOVSTOSW $src)>; +def : Pat<(f32 (bitconvert i32:$src)), (MOVWTOS $src)>; +def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>; +def : Pat<(f64 (bitconvert i64:$src)), (MOVXTOD $src)>; } // Predicates = [HasVIS3] diff --git a/llvm/test/CodeGen/SPARC/bitcast.ll b/llvm/test/CodeGen/SPARC/bitcast.ll new file mode 100644 index 0000000000000..d5fb994a0f0fe --- /dev/null +++ b/llvm/test/CodeGen/SPARC/bitcast.ll @@ -0,0 +1,139 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=vis3 | FileCheck %s -check-prefix=VIS3 + +define i32 @stow(float %0) nounwind { +; V9-LABEL: stow: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: st %f1, [%sp+2187] +; V9-NEXT: ld [%sp+2187], %o0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: stow: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movstouw %f1, %o0 + %2 = bitcast float %0 to i32 + ret i32 %2 +} + +define zeroext i32 @stouw(float %0) nounwind { +; V9-LABEL: stouw: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: st %f1, [%sp+2187] +; V9-NEXT: ld [%sp+2187], %o0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: stouw: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movstouw %f1, %o0 + %2 = bitcast float %0 to i32 + ret i32 %2 +} + +define signext i32 @stosw(float %0) nounwind { +; V9-LABEL: stosw: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: st %f1, [%sp+2187] +; V9-NEXT: ldsw [%sp+2187], %o0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: stosw: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movstosw %f1, %o0 + %2 = bitcast float %0 to i32 + ret i32 %2 +} + +define float @wtos(i32 %0) nounwind { +; V9-LABEL: wtos: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: st %o0, [%sp+2187] +; V9-NEXT: ld [%sp+2187], %f0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: wtos: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movwtos %o0, %f0 + %2 = bitcast i32 %0 to float + ret float %2 +} + +define float @uwtos(i32 zeroext %0) nounwind { +; V9-LABEL: uwtos: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: st %o0, [%sp+2187] +; V9-NEXT: ld [%sp+2187], %f0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: uwtos: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movwtos %o0, %f0 + %2 = bitcast i32 %0 to float + ret float %2 +} + +define float @swtos(i32 signext %0) nounwind { +; V9-LABEL: swtos: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: st %o0, [%sp+2187] +; V9-NEXT: ld [%sp+2187], %f0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: swtos: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movwtos %o0, %f0 + %2 = bitcast i32 %0 to float + ret float %2 +} + +define i64 @dtox(double %0) nounwind { +; V9-LABEL: dtox: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: std %f0, [%sp+2183] +; V9-NEXT: ldx [%sp+2183], %o0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: dtox: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movdtox %f0, %o0 + %2 = bitcast double %0 to i64 + ret i64 %2 +} + +define double @xtod(i64 %0) nounwind { +; V9-LABEL: xtod: +; V9: ! %bb.0: +; V9-NEXT: add %sp, -144, %sp +; V9-NEXT: stx %o0, [%sp+2183] +; V9-NEXT: ldd [%sp+2183], %f0 +; V9-NEXT: retl +; V9-NEXT: add %sp, 144, %sp +; +; VIS3-LABEL: xtod: +; VIS3: ! %bb.0: +; VIS3-NEXT: retl +; VIS3-NEXT: movxtod %o0, %f0 + %2 = bitcast i64 %0 to double + ret double %2 +} `````````` </details> https://github.com/llvm/llvm-project/pull/135716 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
