https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/137606
>From 57a31e183dc8cf8b291768330f628ede741d98d2 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng <dtcxzyw2...@gmail.com> Date: Thu, 24 Apr 2025 00:12:30 +0800 Subject: [PATCH] [InstCombine] Do not fold logical is_finite test (#136851) This patch disables the fold for logical is_finite test (i.e., `and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf`). It is still possible to allow this fold for several logical cases (e.g., `stripSignOnlyFPOps(RHS0)` does not strip any operations). Since this patch has no real-world impact, I decided to disable this fold for all logical cases. Alive2: https://alive2.llvm.org/ce/z/aH4LC7 Closes https://github.com/llvm/llvm-project/issues/136650. (cherry picked from commit 8abc917fe04140b6c6088a67e0398f637efde808) --- .../InstCombine/InstCombineAndOrXor.cpp | 4 ++- llvm/test/Transforms/InstCombine/and-fcmp.ll | 28 +++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index ca8a20b4b7312..ebb84d177a832 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -1475,7 +1475,9 @@ Value *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS, } } - if (IsAnd && stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) { + // This transform is not valid for a logical select. + if (!IsLogicalSelect && IsAnd && + stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) { // and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf // and (fcmp ord x, 0), (fcmp u* fabs(x), inf) -> fcmp o* x, inf if (Value *Left = matchIsFiniteTest(Builder, LHS, RHS)) diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll index c7bbc8ab56f9a..ec1b6ad2ea168 100644 --- a/llvm/test/Transforms/InstCombine/and-fcmp.ll +++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll @@ -4990,6 +4990,34 @@ define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) { ret i1 %and } +define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, half %y) { +; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign_logical_select( +; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]]) +; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000 +; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[COPYSIGN_X]], 0xH7C00 +; CHECK-NEXT: [[AND:%.*]] = select i1 [[ORD]], i1 [[CMP]], i1 false +; CHECK-NEXT: ret i1 [[AND]] +; + %copysign.x = call half @llvm.copysign.f16(half %x, half %y) + %ord = fcmp ord half %x, 0.0 + %cmp = fcmp uge half %copysign.x, 0xH7C00 + %and = select i1 %ord, i1 %cmp, i1 false + ret i1 %and +} + +define i1 @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(half %x) { +; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select( +; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) +; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00 +; CHECK-NEXT: ret i1 [[AND]] +; + %copysign.x = call nnan half @llvm.fabs.f16(half %x) + %ord = fcmp ord half %x, 0.0 + %cmp = fcmp uge half %copysign.x, 0xH7C00 + %and = select i1 %ord, i1 %cmp, i1 false + ret i1 %and +} + define i1 @isnormal_logical_select_0(half %x) { ; CHECK-LABEL: @isnormal_logical_select_0( ; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
