================
@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
- Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
----------------
sdesmalen-arm wrote:
```llvm.partial.reduce(nxv2i64 %acc, mul(zext(nxv16i8 %a) -> nxv16i64,
zext(nxv16i8 %b) -> nxv16i64))```
This case can be lowered with the correct support in selectiondag (see
https://github.com/llvm/llvm-project/pull/130935#discussion_r2068162662)
I'd argue that this function will need a bit of a rewrite anyway once we get
proper support in SelectionDAG for legalising these operations, so I wouldn't
bother changing that in this PR.
https://github.com/llvm/llvm-project/pull/136173
_______________________________________________
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
