llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc Author: Koakuma (koachan) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/138401.diff 6 Files Affected: - (modified) llvm/lib/Target/Sparc/Sparc.td (+5-2) - (modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (+17) - (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+4) - (modified) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+20-1) - (modified) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+20-1) - (added) llvm/test/MC/Sparc/sparc-ua2007.s (+30) ``````````diff diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 0d66a03fd941d..93c3098bd89fe 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -52,6 +52,9 @@ def FeatureVIS3 def FeatureUA2005 : SubtargetFeature<"ua2005", "IsUA2005", "true", "Enable UltraSPARC Architecture 2005 extensions">; +def FeatureUA2007 + : SubtargetFeature<"ua2007", "IsUA2007", "true", + "Enable UltraSPARC Architecture 2007 extensions">; def FeatureLeon : SubtargetFeature<"leon", "IsLeon", "true", "Enable LEON extensions">; @@ -160,10 +163,10 @@ def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureVIS3, - FeatureUA2005]>; + FeatureUA2005, FeatureUA2007]>; def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureVIS3, - FeatureUA2005]>; + FeatureUA2005, FeatureUA2007]>; // LEON 2 FT generic def : Processor<"leon2", LEON2Itineraries, diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td index 4ff902b190a3b..2998f53ef2dbc 100644 --- a/llvm/lib/Target/Sparc/SparcInstrFormats.td +++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td @@ -260,6 +260,23 @@ multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, itin>; } +// 4-operand instructions. +class F3_4<bits<6> op3val, bits<4> op5val, dag outs, dag ins, + string asmstr, list<dag> pattern = [], InstrItinClass itin = NoItinerary> + : F3<outs, ins, asmstr, pattern, itin> { + bits<4> op5; + bits<5> rs3; + bits<5> rs2; + + let op = 2; + let op3 = op3val; + let op5 = op5val; + + let Inst{13-9} = rs3; + let Inst{8-5} = op5; + let Inst{4-0} = rs2; +} + class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> : InstSP<outs, ins, asmstr, pattern, itin> { diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index a220e0379213c..eb6485eaa3d98 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -51,6 +51,10 @@ def HasVIS3 : Predicate<"Subtarget->isVIS3()">, def HasUA2005 : Predicate<"Subtarget->isUA2005()">, AssemblerPredicate<(all_of FeatureUA2005)>; +// HasUA2007 - This is true when the target processor has UA 2007 extensions. +def HasUA2007 : Predicate<"Subtarget->isUA2007()">, + AssemblerPredicate<(all_of FeatureUA2007)>; + // HasHardQuad - This is true when the target processor supports quad floating // point instructions. def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td index d883e517db89d..a1bfcc3dbb652 100644 --- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -7,9 +7,15 @@ //===----------------------------------------------------------------------===// // // This file contains instruction formats, definitions and patterns needed for -// UA 2005 instructions on SPARC. +// UA 2005 and UA 2007 instructions on SPARC. //===----------------------------------------------------------------------===// +// Convenience template for 4-operand instructions +class FourOp<string OpcStr, bits<6> op3val, bits<4> op5val, + RegisterClass RC> + : F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3), + !strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>; + // UltraSPARC Architecture 2005 Instructions let Predicates = [HasUA2005] in { let hasSideEffects = 1 in @@ -19,3 +25,16 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> { let Inst{18-0} = 0; } } // Predicates = [HasUA2005] + +// UltraSPARC Architecture 2007 Instructions +let Predicates = [HasUA2007] in { +def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>; +def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>; +def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>; +def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>; + +def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>; +def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>; +def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>; +def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>; +} // Predicates = [HasUA2007] diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt index dc3d196091c6b..b6a48ab56c9d9 100644 --- a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt +++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt @@ -1,6 +1,25 @@ -# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005,+ua2007 | FileCheck %s ## UA 2005 instructions. # CHECK: allclean 0x85,0x88,0x00,0x00 + +## UA 2007 instructions. + +# CHECK: fmadds %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4a,0x23 +# CHECK: fmaddd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x08,0x42 +# CHECK: fmsubs %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4a,0xa3 +# CHECK: fmsubd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x08,0xc2 +# CHECK: fnmadds %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4b,0xa3 +# CHECK: fnmaddd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x09,0xc2 +# CHECK: fnmsubs %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4b,0x23 +# CHECK: fnmsubd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x09,0x42 diff --git a/llvm/test/MC/Sparc/sparc-ua2007.s b/llvm/test/MC/Sparc/sparc-ua2007.s new file mode 100644 index 0000000000000..6b41f929a75da --- /dev/null +++ b/llvm/test/MC/Sparc/sparc-ua2007.s @@ -0,0 +1,30 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2007 --implicit-check-not=error: +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2007 -show-encoding | FileCheck %s --check-prefixes=UA2007 + +!! UA 2007 instructions. + +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0x23] +fmadds %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0x42] +fmaddd %f0, %f2, %f4, %f6 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0xa3] +fmsubs %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0xc2] +fmsubd %f0, %f2, %f4, %f6 + +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0xa3] +fnmadds %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0xc2] +fnmaddd %f0, %f2, %f4, %f6 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0x23] +fnmsubs %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0x42] +fnmsubd %f0, %f2, %f4, %f6 `````````` </details> https://github.com/llvm/llvm-project/pull/138401 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
